user9785232
Reputation:
Signal initialization VHDL
I have an entity which has this
TEMPERATURE: in STD_LOGIC_VECTOR(7 downto 0);
as one of the inputs and I need a signal that has the initial value TEMPERATURE. In the entity architecture I've declared the signal
signal temp:STD_LOGIC_VECTOR(7 downto 0):=TEMPERATURE;
but when simulating temp remains UU(unassigned). How do I fix this?
Upvotes: 3
Views: 605
Answers (0)
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