CODEWITHSUNDEEP
specmane
Halona
Halona

Reputation: 1485

Specman e: Is there a way to connect a simple_port's hdl_path to negated verilog port?

I have a signal_map with reset port. Many environments use this signal_map unit. The problem is that the reset port is always active low, but in one environment it is active high. There is already a lot of generic logic for all the environments that refers to the reset port as active low, that I want to use as is. Can I to connect the port to a negated verilog port (it will solve all my problems)? Something like this:

keep reset_port.hdl_path() == not "reset_port_in_verilog";

Additional complication: The signal_map unit already has hdl_path, i.e. the actual reset_port.hdl_paht() is "~my_design_module.some_long_path.reset_port_in_verilog"

What would you do? Thank you for any help

Upvotes: 0

Views: 504

Answers (2)

user3467290
user3467290

Reputation: 781

i think the only solution would be to have different event. maybe something like this - 

type env_name_t : [ENV_0, ENV_1, ENV_2];

// for most monitors:
unit monitor {
    name : env_name_t;
    !smp : signal_map;
    event reset is rise(smp.reset_sig$);
};

extend ENV_1 monitor {
    event reset is only fall(smp.reset_sig$);
};

Upvotes: 0

user3467290
user3467290

Reputation: 781

do you mean that in most of your environments, you would like to have something like

event reset is fall(reset_port$);

and in one env, have

event reset is only rise(reset_port$);

?

Upvotes: 0

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