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veriloghdl
Adhamzhon Shukurov
Adhamzhon Shukurov

Reputation: 713

Verilog: proper way of connecting ports

Assume there are two different modules (first_module, second_module). Both of the modules are synchronized with clock signal. first_module has the following structure:

module first_module(
input clk,
input reset_n,
input in1,
output reg out1,
output reg out2
);

//******** some verilog codes *********

endmodule

And second_module has similar structure:

module second_module(
input clk,
input reset_n,
input in1,
input in2,
output reg out1
);

//******** some verilog codes *********

endmodule

And then there is a module called top_module which uses instances of both modules:

module top_module(
input clk,
input reset_n,
input insignal1,
input insignal2,
output outsignal1,
output outsignal2
);

first_module fm1(
  .clk(clk),
  .reset_n(reset_n),
  .in1(insignal1),
  .out1(outsignal1),
  .out2(<connection1>) // to be connected to the connection2 
);

second_module sm1(
  .clk(clk),
  .reset_n(reset_n),
  .in1(insignal2),
  .in2(<connection2>), // to be connected to the connection1
  .out1(outsignal2)
);    

endmodule

The aim is to connect connection1 to connection2. According to my knowledge (if it is correct), we can either declare a single wire (let its name be connection) and replace both <connection1> and <connection2> with it, or we can declare two distinct wires connection1 and connection2, then:

assign connection2 = connection1;

And connect them accordingly.

Upvotes: 1

Views: 4007

Answers (1)

Oldfart
Oldfart

Reputation: 6269

Yes there is a difference. But not in your specific case.

Using a connection directly makes that is can be uni-directional or bi-directional depending on what the underlying ports in the module are.

But assign connection2 = connection1; is only uni-directional.

Thus between bi-directional ports should use direct connections or you should only use bi-directional Verilog constructs between them. The assign ... is not one of them.

But in you case the signal is uni-directional so it does not matter.

Note that modern FPGAs no longer have on-chip bi-directional buses. (At least I don't know one that has). Also in chip design on-chip buses are strongly discourage or outright forbidden by the manufacturers.
Therefore bi-directional signals are normally only present in the test-bench. As that does not get synthesized your question does not apply there.

Last but not least: In HDL design I would strongly discourage from changing the name of a signal for no apparent reason. Having the same name throughout the design makes it easier to debug and trace your signals post-synthesis.

Upvotes: 1

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