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verilogsystem-veriloghdlasic
Wynn
Wynn

Reputation: 29

SystemVerilog : Port connection based on parameter

I'm trying to instantiate multiple copies of a module using a generate. However, these multiple copies have a different output type (depending on a parameter). Is there a way to conditionally connect an output port. eg:

module #(parameter type OUT_TYPE = logic[31:0]) myModule (
   input ....
   output OUT_TYPE mod_out
);

Calling module , note that out_a, out_b, out_c are different types

generate for (genvar g=0; g<4; g++) begin
    localparam type g_TYPE = g==0 ? logic[31:0] : (g==1 ? logic[15:0] : logic[7:0]);
    myModule #(.OUT_TYPE(g_TYPE)) inst_myModule (
      .
      .
      if (g==0)
         .mod_out(out_a)
      else if (g==1)
         .mod_out (out_b)
      else
         .mod_out (out_c)
    );
end endgenerate

Upvotes: 1

Views: 695

Answers (1)

Serge
Serge

Reputation: 12384

No, you cannot do it this way. However, generate blocks allow you to fully instantiate the module:

for (genvar g=0; g<4; g++) begin: loopblk
   if (g == 0) begin
       typedef logic[31:0] g_TYPE;
       myModule#(.OUT_TYPE(g_TYPE)) inst_myModule(.mod_out(out_a));
   end
   else if (g == 1) begin
      myModule #(.OUT_TYPE(logic[15:0])) inst_myModule(.mod_out(out_b));
   end
   else 
      ...
end

Upvotes: 2

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