CODEWITHSUNDEEP
verilog
pedro
pedro

Reputation: 31

Leaving some bits in the port vector disconnected. Verilog module instantiation

Lets say I have a Verilog module with bit vector ports. How do I instantiate it with some bits left unconnected?

I tried something like this but it didn't work:

module sub (in,out)
input [3:0] in;
output [3:0] out;
endmodule

module top;
wire [1:0] a1;
wire [1:0] c1;

sub Sub1(
.in[2:1](a1[1:0]),
.out[2:1](c1[1:0])
 ); 
endomdule

Upvotes: 2

Views: 9824

Answers (4)

Harsha
Harsha

Reputation: 31

Found LRM reference on why you cannot connect parts of ports. LRM 1800-2012 Section 23.3.2.2 Connecting module instance ports by name:

The port_name shall be the name specified in the module declaration. The port name cannot be a bit-select, a part-select, or a concatenation of ports.

Upvotes: 3

jiangwl
jiangwl

Reputation: 1

My code connect 4-bits to module's 8-bit outputs, upper/lower even middle part. It does work, but what the hell is the 's'(or anything)? It works in both Quartus Prime 18.0pro and Lattice Diamond 3.10(Symplify Pro).

module dff8
(
    input clk,
    input [7:0] a,
    output reg [7:0] b
);
    always @ (posedge clk) begin
        b <= a;
    end
endmodule

module top
(
    input clk,
    input [7:0] x,
    output [3:0] y,
    output [3:0] z
);

    dff8 u0 (.clk(clk), .a(x), .b({y,s,s,s,s}));
    dff8 u1 (.clk(clk), .a(x), .b({s,s,s,s,z}));
endmodule

Upvotes: 0

dave_59
dave_59

Reputation: 42616

It would be much easier to just declare signals of the correct size and use a continuous assignment

module top;
  wire [1:0] a1;
  wire [1:0] c1;

  wire [3:0] pin;
  wire [3:0] pout;

  assign pin[2:1] = a1;
  assign c1 = pout[2:1];
  sub Sub1(
           .in(pin),
           .out(pout)
          ); 
endomdule

In general, it is not a good idea to leave input ports floating. You could use a concatenation in the assignment, or directly in the port connection. 

sub Sub1(
               .in({1'b0,a1,1'b0}),
               .out({pout[3],c1,pout[0]})
              );

SystemVerilog has a net aliasing construct that makes thing even simpler

module top;
  wire [3:0] pin;
  wire [3:0] pout;

  alias pin[2:1]  = a1;
  alias pout[2:1] = c1;
  sub Sub1(
           .in(pin),
           .out(pout)
          ); 
endomdule

Upvotes: 3

Serge
Serge

Reputation: 12344

you cannot connect/disconnect parts of a port. You can do it with the whole port though. so, in your case you nedd to split your port in several parts, something like the following:

module sub (in1, in2, out1, out2);
   input [2:1] in1;
   input [1:0] in2;
   output [2:1] out1;
   output [1:0] out2;
endmodule

module top;
   wire [1:0] a1;
   wire [1:0] c1;

   sub Sub1(
    .in1(a1[1:0]),
    .in2(),
    .out1(c1[1:0]),
    .out2()
    ); 
endmodule

Upvotes: 1

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