CODEWITHSUNDEEP
verilogfpgaquartus
Vladimir T
Vladimir T

Reputation: 866

Declare a port in Verilog where some bits are inputs and some are outputs

In verilog for Cyclone 3 I want to declare a port where some pins are inputs and some are outputs, in many examples in web i see that a port is defined like 

input wire [0:10]p;

but what to do if i need bit0 being an input of the IC, while others be an output. Tried like this and some other different variants, but every time i get errors from the compiler. Notice that IO[1] unused in code but present in "Assignment editor".

module main(
      tx,
      rx,
      IO[0],
      IO[2]
     );
output wire tx;
input wire rx;
input wire IO[0];
output wire IO[2];

assign IO[2] = rx;
assign tx = IO[0];

endmodule

Upvotes: 1

Views: 2128

Answers (3)

osama zeeshan
osama zeeshan

Reputation: 29

Since the top level module is not instantiated per se, it doesn't seem using port expressions can work here.

One thing you should try is to change the name of the pins in the pin assignment file (.csv I think) you are loading into Quartus to program your fpga. Give the different pins different names there, e.g. not In[0] or In[1], but rather in0, in1 and so on.

Upvotes: 1

dave_59
dave_59

Reputation: 42616

You can use a port_expression. This separates the name of the port from the signals (or expression of signals) connected to the port. You might recognize this syntax when creating a module instance, but it has always been available for a module declaration as well in Verilog

module m(input .rx(a[0]), output .tx(a[1]));

  wire [1:0] a;
endmodule

module top;
  wire  a,b;  
  m m1(.rx(a),.tx(b));
endmodule

Upvotes: 3

Serge
Serge

Reputation: 12344

there is no way in verilog to declare different directions to different bits of a single vector port. The direction works on the whole declaration of a port. The only way to do it is to split the single port into multiple ports with different names, e.g.

 module main(
  output wire tx,
  input wire rx,
  output wire out,
  input wire in
 );

Then, when you instantiate it, you can define which bits goes where:

 main inst(.tx(tx), .rx(rx), .out(IN[0]), .in(IN[2]);

Upvotes: 1

Related Questions