CODEWITHSUNDEEP
portverilogsystem-verilog
TSP
TSP

Reputation: 111

verilog how to connect array of ports

I just encountered a problem with respect to assigning the ports of one of my modules to standard ports like SW[0].

I have two modules:

module top(SW, LEDR);
input [3:0]SW;
output [3:0]LEDR;

bottom b0 (
.in(SW[3:0]); // I am planning to associate SW[0] to in[0], SW[1] to in[1] etc.
.out(LEDR[0]);
);
endmodule


module bottom(in[3:0], out);
    input [3:0]in;
    output out;
    assign out = in[0] | in[1] | in[2];
endmodule

.in(SW[3:0]); // I am planning to associate SW[0] to in[0], SW[1] to in[1] etc.

What I did was wrong, and Verilog could not compile it. Any advice please?

Upvotes: 1

Views: 2508

Answers (2)

toolic
toolic

Reputation: 62236

The semicolons are incorrect syntax for port connections. Separate each port with a comma (and nothing at the end). Also, get rid of [3:0] in the port list in the bottom module.

module bottom(in, out);
input [3:0]in;
output out;
assign out = in[0] | in[1] | in[2];
endmodule

module top(SW, LEDR);
input [3:0]SW;
output [3:0]LEDR;

bottom b0 (
.in(SW[3:0]),
.out(LEDR[0])
);
 endmodule

Upvotes: 1

dave_59
dave_59

Reputation: 42788

This could should work for you

module top(
           input [3:0] SW,
           output [3:0]LEDR
           );
  bottom b0 (
            .in(SW),
            .out(LEDR[0])
            );
endmodule

module bottom(
              input [3:0] in,
              output out
              );
assign out = {<<{in}}; // bit-reverse 
endmodule

Pay attention to the syntax for port declarations and port connections.

Upvotes: 1

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