CODEWITHSUNDEEP
verilog
Awais Hussain
Awais Hussain

Reputation: 442

Passing an array to a named port connection

If I am sending some parameters to any module in verilog like:

SUM( .a(a), .b(b), .out(out));

It will work fine. What if I want to pass an array as input or want to take arrays as output? For example:

integer  a=10;
  integer  b=20;
  integer  c[2:0]={2,4,6};
  integer  d=0;

any module(.input1(a), .input2(b), .input3(c),.....)

But it will give error that "cannot access memory c directly".

So, how can I send or receive an array in named port connection?

Upvotes: 0

Views: 1133

Answers (1)

Morgan
Morgan

Reputation: 20554

Inputs can be arrays from SystemVerilog 2009. Verilog 1995, 2001 and 2005 do not support array ports.

module dut(
  input [7:0] a [3:0]
);

endmodule

Upvotes: 1

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