CODEWITHSUNDEEP
vhdlspecman
user3444042
user3444042

Reputation: 21

How to connect a simple_port to a concatenation of VHDL signals?

I would like to have an out simple_port bound to multiple VHDL std_logic_vectors. More specifically , i want to connect a 10 bit simple port to two 5 bit buses so that they both construct a 10 bit vector to which i can write to from Specman.

i was trying to do that in the hdl_path() but I got a VHDL compiler error when compiling the VHDL stub.

   keep port.hdl_path="A & B"

where A and B are 5 bit std_logic_vectors.

Upvotes: 0

Views: 721

Answers (1)

yuvalg
yuvalg

Reputation: 331

The ability to connect a simple_port to a concatenation of HDL signals is supported when using verilog, using the hdl_expression() port attribute. This even appears in the hdl_expression() document:

http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=/sn_integ/sn_integ14.1/vlog_hdl_expr_simple.html

However, the hdl_expression() port attribute is not supported in ports that have a VHDL agent. A way to work around this is by defining two simple ports each with the appropriate vector size as shown in this example:

p0: out simple_port of uint(bits:5) is instance;
p1: out simple_port of uint(bits:5) is instance;
keep p0.hdl_path()=="bus1"; 
keep p1.hdl_path()=="bus2"; 

p_top:uint(bits:10);

event write_to_p_top is change(p_top)@sys.any;

on write_to_p_top {
        p1$=p_top[4:0];
        p2$=p_top[9:5]
    };

In your code, all you need to do is to assign values to the top variable 'p_top'. this will trigger the writing sequence to the actual ports with the appropriate values.

Note : this could be generalized to any number of ports using a list of simple_port

Upvotes: 2

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