CODEWITHSUNDEEP
verilogfpgaclockregister-transfer-level
tnet
tnet

Reputation: 627

Clock Conversion for RTL Verilog (FPGA) Synthesizable Code

Converting 12 MHz system clock signal on FPGA to 1 MHz Signal output at a 50% duty cycle.

I understand that I need to divide by 2 @ 50/50 duty cycle to get 6 MHz, and then divide by 2 again to get to 3 MHz, and then divide by 3 to get to 1 MHz. Is this the correct method?

Also, how would I implement this in RTL Verilog code?

Upvotes: 1

Views: 583

Answers (1)

user149341
user149341

Reputation:

Is this the correct method?

No. First, operating on clocks in logic is often difficult to route appropriately, especially in multiple stages. Second, it is especially difficult to divide a clock by 3 and get a 50% duty cycle without either negative-edge or DDR flip-flops, both of which are often unavailable in FPGA fabric.

The correct method is to use your FPGA's clocking resources. Most modern FPGAs will have one or more onboard DLLs or PLLs which can be used to manage clock signals.

On Xilinx parts, these resources are known as the DCM, PLL, and/or MMCM, and can be instantiated using the ClockGen IP core.

On Altera/Intel parts, these resources can be configured through the PLL and other megafunctions.

On Lattice parts, these resources are known as the sysCLOCK PLL, and can be configured using IPexpress.

Upvotes: 2

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