Reputation: 1405
I am trying to build up a self made package for a VHDL project using Vivado and am having an error when I add more than one type declaration.
package TypeDef is
type IntCommand is (meW, meA, meO, meB);
-- type TestType is array (0 to 3) of STD_LOGIC;
type Rec is record
inst : IntCommand;
num1 : STD_LOGIC_VECTOR(3 downto 0);
num2 : STD_LOGIC_VECTOR(3 downto 0);
end record Rec;
end package TypeDef;
If I comment out the line that is commented out with the 'TestType' the package is able to work all the way through to simulation. However, if I uncomment that line of code or add in any other variation of type the design has an error when attempting to simulate. The error on the elaborate step.
Cheers,
Upvotes: 1
Views: 1270
Reputation: 1405
After searching around for the error I found it to be rather simple to fix. I only needed to edit and then save the main file. The error message found in 'elaborlate.log' was 'core.vdb needs to be re-saved since xil_defaultlib.typedef changed'.
Upvotes: 2