CODEWITHSUNDEEP
stringparametersmacrosverilog
Mayur Anvekar
Mayur Anvekar

Reputation: 23

Accessing a node in code using Verilog define macros

Is their a possibility to access a node in the code using a define macro via string parameters

e.g. 

module design
  (
   input logic signal_in_1_temp,
   input logic signal_in_2_temp
   );
endmodule

module tb_top;

   parameter string signal_names[0:1] = {"in_1","in_2"};

   i_design design(.signal_in_1_temp(0),.signal_in_2_temp(0));

   `define IN_SIG(IN_NAME,VAL)\

   force i_design.signal_\``IN_NAME\``_temp = VAL; 

   initial begin
      \`IN_SIG(signal_name[0],1);
      \`IN_SIG(signal_name[1],0);
   end

endmodule

In the above the two inputs of the design would need to be accessed via a parameter list and then a macro ...

Compiling the above gives error .... I would want to know if we can access the nodes status or drive them based on the above means ..

The idea is to have a dynamic parameter list given and then to know the status of that list or drive them based on need....

Any suggestions ... please

Upvotes: 0

Views: 791

Answers (2)

Serge
Serge

Reputation: 12354

No, you cannot do it with strings, but you can do it with regular macro arguments.

here is a working example:

`define A(B) \
$display(sig_``B``_sig);

module top;
  logic sig_x_sig, sig_hello_sig;

  initial begin
    `A(x)
    `A(hello)
  end
endmodule

do not use \ as in your code and do not use empty lines in macro definitions.

Upvotes: 0

dave_59
dave_59

Reputation: 42673

No, you cannot use string names within the language to build identifier names. Verilog does have a C interface (called VPI) that allows you to access signals by signal name, but that comes at a performance cost which means the signal cannot have certain optimizations and must remain intact.

SystemVerilog has a bind construct that allows you to attach functionality to signals deep inside your design. I wrote a DVCon paper about it.

Upvotes: 0

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