CODEWITHSUNDEEP
genericsvhdlfpga
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Reputation: 133

In VHDL, what does RHS of generic map assignment refer to?

Based on my understanding of VHDL, a port map declaration will be:

signal reset_n : std_logic;

...

port map (
    ...
    reset_n => reset_n
);

... where the LHS of the port map assignment is the port name on your component and the RHS is a signal you've declared above.

But for a generic map, what does the RHS refer to? 

...
generic map (
    ...
    baud_rate => baud_rate
);

The LHS is the generic field in the entity to be written to by whatever the RHS specifies (right?), the VHDL way of passing a value into your generic. But if the RHS is not declared as a signal, what is being assigned/wired to the LHS? What is going on under the hood?

Upvotes: 0

Views: 674

Answers (1)

Paebbels
Paebbels

Reputation: 16249

At first, the LHS is called the formal and the RHS is called the actual.

The formal refers to the constant you declared in your entity.

entity foo is
  generic (
    constant baud_rate : T_BAUD
  );
end entity;

The actual is associated in a generic map to a formal. As in your case the actual is a constant, you can either associate:

  • another generic constant from a higher layer
  • a constant declared in an architetcure declarative region or a global constant declared in a package
  • an expression, including a literal.

Examples:

entity e is
  generic (
    baudrate : T_BAUD
  );
end entity;

architecture a of e is
  constant BR : T_BAUD := 100 kBd;
begin
  inst1: entity work.foo
    generic map (
      baud_rate => baudrate
    );
  inst2: entity work.foo
    generic map (
      baud_rate => BR
    );
  inst3: entity work.foo
    generic map (
      baud_rate => 115.2 KBd
    );
end architecture;

Upvotes: 2

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