CODEWITHSUNDEEP
verilogsystem-veriloghdlxilinx-ise
yildizabdullah
yildizabdullah

Reputation: 1971

How to access Verilog genvar generated instances and their signals

I need to initialize arrays in generated instances via generate block in Verilog. I'm trying to use the syntax below, however, I get an error as

External reference foo[0].bar.array[0] remains unresolved.

in Xilinx ISE.

    integer i, j;
    initial begin
        // initialization of arrays
        for(i=0; i<(2**7); i=i+1) begin
            valid_array[i] = 0;
            for(j=0; j<N; j=j+1) begin
                foo[j].bar.array[i] = 0;
            end
        end
    end

This is my generate block:

    genvar jj;
    generate
        for(jj = 0; jj < N; jj = jj + 1) begin : foo
            Memory_v3
            #(
                .ADDRESS_WIDTH(INDEX),
                .DATA_WIDTH(TAG)
            ) bar
            (
                .clock(clock),
                .we(we),
                .addr_a(addra),
                .addr_b(addrb),
                .din(din),
                .dout(dout)
            );
        end
    endgenerate

What is the correct way to do this?

Upvotes: 0

Views: 2267

Answers (1)

Serge
Serge

Reputation: 12344

the problem is that foo block gets resolved at compile time. So, the names like foo[0], foo[1] are pre-generated and are compile-time names, they not work with dynamic index resolution at run-time. Therefore foo[j] will not work.

the solution in this case is to use another generate block to initialize them. Something like the following.

 generate
   for(jj = 0; jj < N; jj = jj + 1) begin : foo_init
      initial begin
         // initialization of arrays
         for(i=0; i<(2**7); i=i+1) begin
            foo[jj].bar.array[i] = 0;
         end
      end
   end
endgenerate

Same story is with array of instances. 

FOO bar[3:0](); // array of instances

int i,j;
generate
   for(jj = 0; jj < 4; jj = jj + 1) begin : foo_init
      initial begin
         for(i=0; i<(2**7); i=i+1) begin
            bar[jj].array[i] = 0;
         end
      end
   end
endgenerate

BTW, in system verilog you can avoid using generate/endgenerate pairs:

Upvotes: 1

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