Usman Mani
Usman Mani

Reputation: 77

Most significant bit operand in part-select of vector wire is illegal

I want to make a parameterized FIR filter in verilog on xilinix. This is my code:

module FIRFilter(xInput, clock, reset, filterCoeff, yOutput);
parameter inputBits = 8, lengthOfFilter = 4, coeffBitLength = 8, lengthOfCoeff = lengthOfFilter + 1, outputBitWdth = 2 * inputBits;
input [(coeffBitLength * lengthOfCoeff) - 1 : 0] filterCoeff;
input clock, reset;
input [inputBits - 1 : 0] xInput;
reg [outputBitWdth - 1 : 0] addWires [lengthOfFilter - 1 : 0];
output reg [outputBitWdth - 1 : 0] yOutput;
reg [inputBits - 1 : 0] registers [lengthOfFilter - 1 : 0];
integer i, j;
always @ (posedge clock, posedge reset)
begin
    if(reset)
    begin
        for(i = 0; i < lengthOfFilter; i = i + 1)
        begin
            registers[i] <= 0;
        end
    end
    else
    begin
        registers[0] <= xInput;
        for(i = 1; i < lengthOfFilter; i = i + 1)
        begin
            registers[i] <= registers[i - 1];
        end
    end
end
always @ (posedge clock)
begin
    addWires[0] = filterCoeff[(lengthOfFilter * coeffBitLength) - 1 : (lengthOfFilter - 1) * coeffBitLength] * xInput;
    for(j = 1; j < lengthOfFilter; j = j + 1)
    begin
        addWires[j] = (filterCoeff[((j + 1) * coeffBitLength) - 1 : j * coeffBitLength] * registers[j - 1]) + addWires[j - 1];
    end
    yOutput = (filterCoeff[coeffBitLength - 1 : 0] * registers[lengthOfFilter - 1]) + addWires[lengthOfFilter - 1];
end
endmodule

But I keep getting this error

ERROR:HDLCompilers:109 - "FIRFilter.v" line 33 Most significant bit operand in part-select of vector wire 'filterCoeff' is illegal
ERROR:HDLCompilers:110 - "FIRFilter.v" line 33 Least significant bit operand in part-select of vector wire 'filterCoeff' is illegal
ERROR:HDLCompilers:45 - "FIRFilter.v" line 33 Illegal right hand side of blocking assignment

I searched online for the solution but haven't got any satisfactory answer. Can someone help me with the this?

Upvotes: 0

Views: 2853

Answers (1)

dave_59
dave_59

Reputation: 42623

Verilog does not allow part selects signal[msb:lsb] where msb and lsb are not constants. You can use another construct called an indexed part select where you specify a constant width, but a variable offset signal[offset+:width]

addWires[0] = filterCoeff[(lengthOfFilter * coeffBitLength) +:coeffBitLength] * xInput;

Upvotes: 1

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