CODEWITHSUNDEEP
vhdl
Ethan
Ethan

Reputation: 82

Why am I getting an Inferred Latch Error?

I have been getting the error: [Synth 8-327] inferring latch for variable 'd_reg' at the line address1 <= d(31 DOWNTO 0) for the past hour. I am not sure why I am not getting this error. I have added all variables in my input list to the process, and I have added and else for all the if statements in my code. Those are the two reasons that I know of that give implied latches, but it turns out I a still getting them.

Does anyone see my problem?

PORT (d        : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) := "00000000000000000000000000000000";
     address  : IN    STD_LOGIC_VECTOR(31 DOWNTO 0) ;
     ce_l     : IN    STD_LOGIC ;
     oe_l     : IN    STD_LOGIC ;
     we_l     : IN    STD_LOGIC ;
     results : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --binary for which segments of digit to turn on
     anodesList : INOUT STD_LOGIC_VECTOR(7 downto 0) := "00000000"; --binary for which annode to turn on
     clk      : IN    STD_LOGIC) ;

(Part of) my code:

SIGNAL address1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := "00000000000000000000000000000000";
SIGNAL check : STD_LOGIC_VECTOR(0 DOWNTO 0) := "0";
writeprocess:PROCESS(clk, ce_l,we_l, address1, check)
   begin
      IF (clk = '1' AND clk'event) THEN
          IF(check = "1") THEN
             IF (ce_l = '0' AND we_l = '0') THEN
                address1 <= d(31 DOWNTO 0); 
             ELSE
                address1 <= address1;
             END IF;
           ELSE
                address1 <= address1;
           END IF;
       ELSE
           address1 <= address1;
       END IF;
   END PROCESS writeprocess ;

Upvotes: 3

Views: 6430

Answers (1)

Charles Steinkuehler
Charles Steinkuehler

Reputation: 3365

You typically get inferred latches when you don't provide updated assignments for a signal in all possible variants of an if/else or case statement in a process.

In your case, your process statement includes 5 signals, but only two matter (clk and address1). You have a well formed synchronous conditional statement for "IF (clk = '1' AND clk'event) THEN", but there is an ELSE clause which likely the cause of your problems. VHDL will leave the value of a signal at it's previous state unless you explicitly modify it, so there is no need for the:

ELSE
   address1 <= address1;

...which I suspect is causing the warnings you're seeing, although it could also be the unnecessary signals in the process sensitivity list. Try a simplified version without the unneeded signals and conditionals:

writeprocess:PROCESS(clk)
   begin
      IF (clk = '1' AND clk'event) THEN
          IF(check = "1") THEN
             IF (ce_l = '0' AND we_l = '0') THEN
                address1 <= d(31 DOWNTO 0); 
             ELSE
                address1 <= address1;
             END IF;
           ELSE
                address1 <= address1;
           END IF;
       END IF;
   END PROCESS writeprocess ;

Upvotes: 3

Related Questions