Can't find the issues and latches are generated

Question

My code generates two latches, could please someone help me finding why? According to Xilinx ISE latches are generated because of "try_counter" which is a counter for how many times you get a numeric sequence wrong. (which is the main point of my code).

I don't know what else to do.

entity moore is
Port ( badgeSx : in  STD_LOGIC;
            badgeDx : in  STD_LOGIC;
            col : in std_logic_vector (1 to 3);
            row : in std_logic_vector (1 to 4);
            clk : in std_logic;
            rst : in std_logic;
            unlock : out  STD_LOGIC
        );
end moore;

architecture Behavioral of moore is
type stato is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9);
    signal current_state,next_state : stato;
    signal badge : std_logic_vector(1 downto 0);
    signal count, new_count: integer range 0 to 28;
    signal temp_unlock : std_logic :='0';
    signal timeover : std_logic :='0';
begin
    badge <= badgeDx & badgeSx; --concatenazione dei badge
--processo sequenziale
    current_state_register: process(clk)
    begin
    if rising_edge(clk) then
        if (rst = '1') then 
            current_state <= s0; 
            count <= 0;
        else 
            current_state <= next_state; 
            count <= new_count;
    end if;
end if;
end process;


process (current_state,badge,col,row,timeover)
    variable try_counter: integer range 0 to 3;
    begin
    case current_state is

    when s0 =>
        try_counter := 0;
        temp_unlock <= '0';
        unlock <='0';
        if(badge ="01" and row = "0000" and col = "000" ) then
            next_state <= s1;
        else 
            next_state <= s0;
        end if;

    when s1 =>
        temp_unlock <= '1';
        unlock <= '0';
        if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
            next_state <= s2;
        elsif (timeover ='1' or badge = "10" or try_counter = 3) then
            next_state <= s0;
        else 
            next_state <= s1;
            try_counter := try_counter +1;
        end if; 

    when s2 => 
        temp_unlock <= '0';
        unlock <='0';
        if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
            next_state <= s2;
        else
            next_state <= s3;
        end if;

    when s3 =>
        temp_unlock <= '1';
        unlock <= '0';
        if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
            next_state <= s4;
        elsif (timeover ='1' or badge = "10" or try_counter = 3) then
            next_state <= s0;
        else 
            next_state <= s1;
            try_counter := try_counter +1;
        end if;

    when s4 =>
        temp_unlock <= '0';
        unlock <='0';
        if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
            next_state <= s4;
        else
            next_state <= s5;
        end if;

    when s5 =>
        temp_unlock <= '1';
        unlock <= '0';
        if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
            next_state <= s6;
        elsif (timeover ='1' or badge = "10" or try_counter = 3) then
            next_state <= s0;
        else 
            next_state <= s1;
            try_counter := try_counter +1;
        end if;

    when s6 =>
        temp_unlock <= '0';
        unlock <='0';
        if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
            next_state <= s6;
        else
            next_state <= s7;
        end if;

    when s7 =>
        temp_unlock <= '1';
        unlock <= '0';
        if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
            next_state <= s8;
        elsif (timeover ='1' or badge = "10" or try_counter = 3) then
            next_state <= s0;
        else 
            next_state <= s1;
            try_counter := try_counter +1;
        end if;

    when s8 =>
        temp_unlock <= '0';
        unlock <='0';
        if (badge = "00" and col ="001" and row = "0001" and timeover = '0') then
            next_state <= s8;
        else
            next_state <= s9;
        end if;

    when s9 =>
        temp_unlock <= '0';
        unlock <= '1';
        if (badge = "10") then
            next_state <= s0;
        else
            next_state <= s5;
        end if;
    when others =>
     next_state <= s0;
    end case;
  end process;

Contatore_TIMER : process(temp_unlock,count)
 begin
   if temp_unlock = '1' then 
          if count = 28 then 
             new_count<=0;
             timeover<='1';
          else
             new_count<=count+1;
             timeover<='0';
          end if;
   else 
       new_count<=0;
       timeover <= '0';
   end if;
   end process;
 end Behavioral;

The code nearly works as expected (I mean it compiles and I don't get any error) but the RTL schematic isn't what it is supposed to be since it synthesises latches in the process.

Answer 1

In the apparently combinatorial process with process (current_state,badge,col,row,timeover), the variable try_counter is used to store information (sequential behaviour), which is only updated when process evaluation is triggered. This will very likely to generate the 2 latches, which matches the value range from 0 to 3 for try_counter.

To fix this, you can define try_counter as a signal, and include it in the sensitivity list for the process.

Having try_counter as a signal will also ease debugging, since the current state can easily be inspected in waveforms.