CODEWITHSUNDEEP
verilogfpgasystem-verilogmodelsim
Taako
Taako

Reputation: 607

Allowing re-declaration of certain parameters inside package for simulation

I have a system that has some timeouts that are on the order of seconds, for the purpose of simulation i want to reduce these to micro- or milli-seconds.

I have these timeouts defined in terms of number of clock cycles of my FPGAs clock. So as an example

package time_pkg

parameter EXT_EN_SIG_TIMEOUT = 32'h12345678;
...
endpackage

I compare a counter against the constant global parameter EXT_EN_SIG_TIMEOUT to to determine if it is the right time to assert an enable signal.

I want have this parameter (as well as a bunch of others) defined in a package called time_pkg in a file called time_pkg.v and I want to use this package for synthesis.

But when I simulate my design in Riviera Pro (or Modelsim) i'd like to have a second parameter defined inside a file called time_pkg_sim.v that is imported after time_pkg.v and overwrites the parameters that share the same name as already defined in time_pkg.

If I simply make a time_pkg_sim.v with a package inside it with the same name (time_pkg) then Riviera complains since i'm trying to re-declare a package that's already been declared.

I don't particularly want to litter my hdl with statements to check if a simulation flag is set in order to decide whether to compare the counter against EXT_EN_SIG_TIMEOUT or EXT_EN_SIG_TIMEOUT_SIM

Is there a standard way to allow re-definition of paramters inside packages when using a simulation tool?

Upvotes: 0

Views: 285

Answers (2)

Tonmoy Roy
Tonmoy Roy

Reputation: 61

It may be a better idea to have a massive ifdef with the simulator falg inside the package. That way your code would not be littered with ifdef everywhere, just concentrated in one place. Moreover, the code inside the modules itself would not need to change.

Upvotes: 1

dave_59
dave_59

Reputation: 42698

No, you can't override parameter in packages. What you can do is have two different filenames that declare the same package with different parameter values, and then choose which one to compile for simulation or synthesis.

Upvotes: 1

Related Questions