CODEWITHSUNDEEP
verilog
Roman Chismar
Roman Chismar

Reputation: 37

Error (10734): Verilog HDL error at m.v(156): cnt is not a constant

I need to write 4 bytes from input pins to different parts of a register depending on a counter, with the code i have now I get this error:
Error (10734): Verilog HDL error at m.v(156): cnt is not a constant
How should I deal with it?

wire wren, rst;     
wire [3:0] abcd;    
reg [31:0] my_reg;    
reg [3:0] cnt;   


always @(posedge wren or posedge rst)   
begin   
   if (rst == 1) 
   begin 
      my_reg <= 0; 
   end    
   else 
   begin   
      if (wren == 1) 
      begin    
         my_reg [4*cnt+3:4*cnt] <= abcd;   
      end   
   end          
end

Upvotes: 0

Views: 1449

Answers (1)

Oldfart
Oldfart

Reputation: 6269

As for your error: you should use the +: syntax [4*cnt +: 4] See here for more information.

Even if that would be semantically allowed your values would be wrong:

  • [4*cnt-1:4*cnt] would give a low:high index e.g. if cnt=1 you get [3:4]

  • [4*cnt-1:4*cnt] gives a negative index if cnt==0 [-1:0] which is outside the range [31:0] of reg.

You probably meant to use [4*cnt+3:4*cnt]

But you have other errors too.

First it is very dangerous to use a keyword for a variable. (reg)

Second you are clocking using a non-clock signal: wren. This creates another clock tree. The normal procedure is to use an if with the standard system clock:

always @(posedge clk or posedge rst)   
begin   
   if (rst == 1) 
   begin 
      my_reg <= 0; 
   end    
   else 
   begin   
      if (wren == 1) 
      begin    
         my_reg [4*cnt +: 4] <= abcd;   
      end   
   end          
end

Upvotes: 2

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