CODEWITHSUNDEEP
fpgaram
Avishai Weizman
Avishai Weizman

Reputation: 1

problem in ram in fpga zynq 7020, someone can give me advice?

Hello I get a strange message when I try to run the MAP, I set the RAM properly and also checked that it uses only 80% of the resources I have on the card. Why do I get this message? Can anyone advise me what to do? And why do I have this message?

The error i got when i try to Synthesize the label "map" to get a bit file

enter image description here - summery of the resources.

enter image description here

ERROR:Place:543 - This design does not fit into the number of slices available in this device due to the complexity of the design and/or constraints.

Unplaced instances by type:

BLOCKRAM 77 (55.0)

Please evaluate the following:

  1. BLOCKRAM u_xyz2lcd_for_test/u_send_to_zedboard/dpr_2/U0/xst_blk_mem_generator/gnativeb mg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.S DP.SIMPLE_PRIM18.ram
  2. BLOCKRAM

Upvotes: 0

Views: 181

Answers (1)

Oldfart
Oldfart

Reputation: 6269

It simply means that you want to use more RAM then the device has.

I suggest you check your resources again and check the amount of memory used.

Your 80% may be LUTs or FFs or you may have read something wrong.

There is another possibility although it is very rare: You memory usage may increase in Place And Route if it has to split the memory over multiple blocks because you have some weird configuration.

This example may not be valid bit it tries to show what can happen:
Suppose you use bit-write enables. Synthesis thinks you have enough memory but PAR has to use a byte for each bit, thus PAR needs to splits the data over more blocks and in the end runs out.

The case where I have seen this was a very complex one with DSPs.

Upvotes: 0

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