CODEWITHSUNDEEP
embeddedverilogsystem-verilogfpga
Abdulkadir Arslan
Abdulkadir Arslan

Reputation: 23

When I add memory clear logic Bram memory turn into distributed ram

I want to create a BRAM that has a data clear logic. With saying that I mean after a reset signal all the data inside of the BRAM needs to be 0.

I coded BRAM in verilog HDL.

(* ram_style = "block" *) 
reg [7:0] mem [511:0];
reg [7:0] data_read = 8'b0;   
             
 always@(posedge clk) begin

        
        if (write_i) begin
             mem[addr_i] <= write_data_i;
        end 
        
        else  begin
              data_read <= mem[addr_i];     
        end

       
 end   
 
 assign read_data_o = data_read;

This code block successfully generates BRAM as netlist can be shown in the following image:

enter image description here

But when I add reset logic to BRAM to clear the data inside of it when reset rises, BRAM memory turns into distributed RAM.

This is the data clear logic I have added:

   if (rst) begin
        
        for(i=0; i<512 ; i= i+1) begin
            mem[i] <= 8'b0;
        end   
          
    end

Netlist after I added clear logic:

enter image description here

What is the reason of this? Why BRAM becomes distributed Ram? Isn't it possible to create a BRAM with data clear logic ?

Upvotes: 1

Views: 296

Answers (1)

Mikef
Mikef

Reputation: 2510

The vendor BRAM macro/primitives/hardware do not support a global clear/write 0, or write anything else using a control signal.
See
https://docs.xilinx.com/v/u/2019.2-English/ug901-vivado-synthesis
section 4 for supported RAM inference coding styles.

There are two ways to accomplish some sort of BRAM initialization or global write.

  1. Use a state machine controller to loop thru all the addresses
    and assign the values needed (write to the ram in a controlled way using RTL to control the address, data, and wr_en)
  2. Use Vivado IP catalog (or ISE Coregen) generated RAM and a .mif/.coe file. The contents of the .mif/.coe get loaded one time when the FPGA is configured.
    More info on using .mif files here:
    https://docs.xilinx.com/r/en-US/ug896-vivado-ip/IP-User-Files-ip_user_files-for-Core-Container

The memory generator GUI provides the opportunity to load a .coe file. The .coe is used for synthesis, .mif file for simulation.

enter image description here

If you want to use the generated IP method see:
https://docs.xilinx.com/v/u/en-US/pg058-blk-mem-gen

My preference is a state machine, so that external files and external IP are not needed.

Upvotes: 3

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