CODEWITHSUNDEEP
vhdlfpga
dem
dem

Reputation: 29

Looping in vhdl

I am writing a code for RSA algorithm . I need to use loop for it to work. But the loop doesn't have definite bound. So it is not sythesizable . Is there any other methods for looping? Please help.

Upvotes: 0

Views: 157

Answers (2)

Martin Thompson
Martin Thompson

Reputation: 16792

You don't need to use a loop, but perhaps you feel it's most convenient?

If you are using the loop to define how much hardware gets built you need to include all the possible hardware (so have a high bound to the loop) and then use some logic to take the output you require from the right place in the hardware so emulate the case of the loop "exiting early"

Alternatively, if you are emulating a software loop in a state machine, then you can keep track of iterations, or a flag for "complete", in a state variable, and use that to move onto the next state when you have performed enough computation.

Upvotes: 1

Matthew
Matthew

Reputation: 13937

The kind of loop is irrelevant. You cannot synthesise a variable amount of hardware. However, for a loop to be synthesisable, it must have a definite upper bound - a maximum number of iterations must be clear to the synthesiser. It is allowed to exit a loop early.

I would recommend you stick to for loops for synthesis. This will make your code more portable.

Upvotes: 3

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