CODEWITHSUNDEEP
vhdluartxilinxvivado
huytergan
huytergan

Reputation: 37

'Opt_Design Error' in Vivado when trying Run Implementation

Trying to make a UART Transmitter to send a data from FPGA to PC; 9600 baudrate, 8-bits, no parity, 1 start & stop bit; I wrote a code with VHDL, run synthesis and simulate it in a way I like it to be. I wanted to see it with BASYS 3 FPGA, After created constraints, Run Implementation issued an error in which its called "Opt_Design Error".

library ieee;
use ieee.std_logic_1164.all;


entity rs232_omo is
generic(clk_max:integer:=10400); --for baudrate


port(

clk : in std_logic;
rst : in std_logic;
start : in std_logic;
input : in std_logic_vector(7 downto 0);
done : out std_logic;
output : out std_logic;
showstates: out std_logic_vector(3 downto 0)
);
end entity;

architecture dataflow of rs232_omo is

type states is (idle_state,start_state,send_state,stop_state);
signal present_state,next_state : states;
signal data,data_next : std_logic;

begin

process(clk,rst)
variable count : integer range 0 to clk_max;
variable index : integer range 0 to 10;
begin

if rst='1' then
    present_state<=idle_state;
    count:=0;
    data<='1';
    done<='0';

elsif rising_edge(clk) then

    present_state<=next_state;
    count:=count+1;
    index:=index+1;
    data<=data_next;

end if;

end process;

process(present_state,data,clk,rst,start)
variable count : integer range 0 to clk_max;
variable index : integer range 0 to 10;
begin

done<='0';
data_next<='1';

case present_state is

    when idle_state =>
        showstates<="1000";
        data_next<='1';

        if start='1' and rst='0' then
            count:=count+1;
            if count=clk_max then
                next_state<=start_state;
                count:=0;
            end if;    
        end if;

    when start_state =>
        showstates<="0100";
        data_next<='0';

        count:=count+1;
        if count=clk_max then
            next_state<=send_state;
            count:=0;
        end if;

    when send_state =>
        showstates<="0010";
        count:=count+1;
        data_next<=input(index);

        if count=clk_max then
            if index=7 then
                index:=0;
                next_state<=stop_state;
            else
                index:=index+1;
            end if;
        count:=0;
        end if;

    when stop_state =>
        showstates<="0001";
        count:=count+1;
        if count=clk_max then
        next_state<=idle_state;
        done<='1';
        count:=0;
        end if;

   end case;
   end process;
   output<=data;

   end architecture;

This's the error message in detail

"[DRC MDRV-1]Multiple Driver Nets:Net done_OBUF has multiple drivers: done_OBUF_inst_i_1/O,and done_reg/Q"

"[Vivado_Tcl 4-78] Error(s) found during DRC. Opt_Design not run."

What would be the reason for this error?

Upvotes: 1

Views: 5747

Answers (1)

Giampietro Seu
Giampietro Seu

Reputation: 816

You are assigning done both in the first and the second process, which is exactly what the implementation is complaining about, you cannot have multiple drivers.

Remove done<='0'; from the first process and it should complete the implementation.

(I didn't check if the rest of the code is doing exactly what you want.)

Upvotes: 1

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