CODEWITHSUNDEEP
verilogsystem-verilogverificationsystem-verilog-assertions
nandeesh v
nandeesh v

Reputation: 127

Why is the following assertion hits only once at the start and fails to go to inactive state and stays in finished state?

enter image description hereFollowing is a assertion property. When o_dc_mode = 1 then o_mod_c_c == rego_dc_c_c. As you can see from the waveform, once the ASK_MOD_DC_MODE_PROPERTY hits the scenario, it stays at "finished" state never goes to inactive state even though o_dc_mode = 0.

property ASK_MOD_DC_MODE; 
@(posedge OSC64MHZ) 
o_dc_mode |->  (o_mod_c_c == rego_dc_c_c);
endproperty

ASK_MOD_DC_MODE_PROPERTY: assert property (ASK_MOD_DC_MODE)
$info("Assertion ASK_MOD_DC_MODE passed");
else
$error("Assertion ASK_MOD_DC_MODE failed");

Upvotes: 1

Views: 1793

Answers (1)

nandeesh v
nandeesh v

Reputation: 127

As you know that in concurrent assertion, the simulator has a performance optimization that disables the evaluation of a single cycle assertion on the cycles where the assertion state is same as in the previous cycle.

For the example in the question:

property ASK_MOD_DC_MODE; 
@(posedge OSC64MHZ)
o_dc_mode |-> ( (o_mod_a_c == rego_dc_a_c) &&  (o_mod_b_c == rego_dc_b_c) && (o_mod_c_c == rego_dc_c_c));
endproperty
ASK_MOD_DC_MODE_PROPERTY: assert property (ASK_MOD_DC_MODE)
$info("Assertion ASK_MOD_DC_MODE passed");
else
$error("Assertion ASK_MOD_DC_MODE failed");

Fig.1 In the above assertion, as soon as the simulator hits the property, it will update the finish_count = 1 (Fig.1) and never updates the state (also the finish_count) unless there is a failure. Fig.2 This optimization can be turned off by using the compilation option ”-abvevalnochange “. You can see the effect in the Fig.2.

Upvotes: 2

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