CODEWITHSUNDEEP
verilogmuxiverilog
Stephen Greer
Stephen Greer

Reputation: 1

MUX in iVerilog: Unable to bind parameter/cannot evaluate genvar expression errors

Will someone please take a look at my code and explain why I am getting these errors. I am brand new to iverilog. This is for a project

Power_ALU.v:13 error: Unable to bind parameter 'select' in 'Power_ALU_tb.ALU8'

Power_ALU.v:13 error: Cannot evaluate genvar conditional expression: (select)==('sd0)

Line 13 is the first line under //INCREMENT

Here is my code

module PowerALU(Out,Cin,s1,s2,s3,A,B);

input [7:0] A,B;
input Cin,s1,s2,s3;
output [7:0] Out;

wire Cout,A_LT_B,A_GT_B,A_EQ_B;
wire [7:0] Sum,And,Or,Xor,Nand,Nor,Xnor;
wire select;
assign select = {s3,s2,s1,Cin};

//INCREMENT
if(select == 0)
begin
    assign B = 8'b00000001;
    RCA8 rca1(Cout,Sum,A,B,Cin);
    assign Out = Sum;
end
//TRANSFER
.
.
.
//EQ
else if(select == 14)
begin
    Comparator8 comp3(A_GT_B,A_LT_B,A_EQ_B,A,B);
    assign Out = {0,0,0,0,0,0,0,A_EQ_B};
end

endmodule

Upvotes: 0

Views: 804

Answers (1)

gatecat
gatecat

Reputation: 1186

If you have an if statement outside of an always (or initial) block, it is interpreted as a generate-if used for selecting different hardware to create at build time. As a result, if the condition is not an elaboration time constant, as here, then the result is a compile error.

You should put your if statements inside an always @* block and remove the assign keyword from the assignments. You will need to move the submodule instances outside of the always block, they can't be turned on or off at runtime.

Upvotes: 1

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