CODEWITHSUNDEEP
verilogmodelsim
William
William

Reputation: 41

Two to one mux in Verilog giving errors for unable to bind for a case statement?

compiler errors:

lastname_dp.v:17: error: Unable to bind parameter sel' in testbench.dpTWOTOONEMUX'

lastname_dp.v:17: error: Cannot evaluate genvar case expression: sel

code:

module twotoonemux(input wire [31:0] input1, input wire [31:0] input2, input wire sel,
output wire [31:0] outputval);
    case(sel)
        0: assign outputval = input1;           //if sel is 0, first input is taken
        1: assign outputval = input2;           //if sel is 1, second input is taken
    endcase
endmodule

testbench

//mux
reg [31:0] input1;
reg [31:0] input2;
reg sel;
wire [31:0] outputval;
twotoonemux dpTWOTOONEMUX(input1,input2,sel,outputval);

//2 to 1 MUX
        input1 = $urandom % 100;
        input2 = $urandom % 100;
        sel = 0;
        #10
        $display("inputs %2d & %2d, sel %1d, output %2d", input1, input2, sel, outputval);
        sel = 1;
        #10
        $display("inputs %2d & %2d, sel %1d, output %2d", input1, input2, sel, outputval);

these are all just blocks of a larger project, if the whole thing is needed please let me know

Upvotes: 1

Views: 160

Answers (1)

Serge
Serge

Reputation: 12354

The case statement in your example could have been a generate block except that a generate block cannot have variables as a select. In your case sel is a variable (input wire sel). So, it is the source of your error(s). It is neither a generate block nor any other legal verilog construct.

If I understand your code correctly, you tried to express something like the following:

   assign outputval = sel ? input1 : input2;

The above should compile correctly.

Upvotes: 2

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