CODEWITHSUNDEEP
verilogmodelsimmultiplexing
Jackkt
Jackkt

Reputation: 65

Illegal assignment expression in continuous assignment. Verilog Octal 2 to 1 Mux

I'm trying to code an Octal (8-bit inputs) 2-to-1 Multiplexer. Here is my code:

module octal2to1mux(input [7:0] a, input [7:0] b, input s, output w);

assign w= (s=1'b0) ? a:
          (s=1'b1) ? b: 1'bx;
endmodule

When I try to compile, I get the following error:

octal2to1mux.sv(3): Illegal assignment expression in continuous assignment.

I just want to get w=a if s=0 and w=b if s=1. a and b are both 8-bit inputs. I use this module twice in the testbench.

Upvotes: 0

Views: 440

Answers (2)

toolic
toolic

Reputation: 62121

The recommended way to code a synthesizable mux is:

module octal2to1mux (input [7:0] a, input [7:0] b, input s, output [7:0] w);
    assign w = (s) ? a : b;
endmodule

It is simpler, easier to understand and fixes your syntax error. Also, if s is X or Z, then w will be X; there is no need to explicitly set it to X.

Note that w must be the same bit width as the a and b inputs.

Upvotes: 1

Light
Light

Reputation: 1316

The output w shall have a width of 8. And as @Serge commented, when comparing, == or === (not synthesizable) should be used.

Upvotes: 0

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