CODEWITHSUNDEEP
verilogsystem-veriloghdlsystem-verilog-assertionsregister-transfer-level
yildizabdullah
yildizabdullah

Reputation: 1971

How to specify sample delay in SystemVerilog covergroup

I need to sample signals in a cover group 1 nanosecond after posedge clock. What is the syntax to do that?

My MWE is as follows:

covergroup DEBUG_CG @ (posedge tb_clock);
  debug_IR : coverpoint dutDevKit.System.debug_1.dmOuter.dmOuter.auto_int_out_0
  {
    bins debug_IR_1 = {1'b1}; 
  }
  debug_ndreset : coverpoint dutDevKit.debug_1.dmOuter.dmOuter.io_ctrl_ndreset
  {
    bins debug_ndreset_1 = {1'b1}; 
  }
endgroup :DEBUG_CG

Upvotes: 0

Views: 506

Answers (1)

Matthew
Matthew

Reputation: 13987

How about:

always @(tb_clock)
  #1 delayed_tb_clock = tb_clock;

covergroup DEBUG_CG @(posedge delayed_tb_clock);

or:

always @(posedge tb_clock) 
  #1 DEBUG_CG0.sample();

covergroup DEBUG_CG;
...
DEBUG_CG DEBUG_CG0 = new();

Upvotes: 2

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