CODEWITHSUNDEEP
system-veriloghdl
Topa
Topa

Reputation: 100

SystemVerilog: Is there a way to get a reg delayed by more than 1 clock cycles in one line?

I have a bunch of signals that I want to delay by x number of cycles so I can easily debug the signals in waveform. Basically I want to make signals for different units aligned together.

I know you can do it this way but that's writing two lines per signal ignoring the for loop and always. Is there a way to do it in 1 line per signal?

logic [3:0] a
logic [3:0] a_delayed [0:X-1]


always @(posedge clk) begin
  a_delayed[0] <= a;
  for(int i=1; i<X;i++)
    a_delayed[i] <= a_delayed[i-1];
end

Edit: Another option is to implement a submodule that performs shift register but I am looking for an option with 1 module only.

Upvotes: 0

Views: 752

Answers (1)

dave_59
dave_59

Reputation: 42738

You can use an unpacked array concatenation

always @(posedge clk) begin
  a_delayed <= {a, a_delayed[0:X-2]};
end

Upvotes: 2

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