CODEWITHSUNDEEP
system-verilog
jkang
jkang

Reputation: 549

SystemVerilog: proper place to put interfaces

I'm wondering if there's a recommended or standard way in which people arrange Interfaces for design in their projects. My project (simplified):

top
top.sv
--includes
----my_intf.sv
----my_pkg.sv
----my_defines.sv
--sub1
----sub1.sv
--sub2
----sub2.sv

I have functions and parameters inside my_pkg.sv:

`include "my_defines.sv"
package my_pkg;
parameter SETTING1 = 5;
parameter SETTING2 = 6;

typedef logic [SETTING1-1:0] my_type1_t;
typedef logic [SETTING2-1:0] my_type2_t;

function my_type1_t sub(input my_type1_t a, b);
  return a - b;
endfunction
endpackage

And my_intf.sv:

interface data_if #(
  parameter type data_t
);

logic vld;
logic ray;
logic data_t data;

modport src(
  output vld, data,
  input rdy
);
modport dst(
  input vld, data,
  output rdy
);
endinterface

My question is, should I `include my_intf.SystemVerilog? What happens when I `include them in multiple design modules? What happens if my_intf.sv uses a definition inside my_pkg.sv? If I include my_pkg.sv inside my_intf.sv, my_pkg.sv will be included multiple times (which causes a warning).

What's everyone's preferred arrangement with this stuff?

Upvotes: 0

Views: 2452

Answers (1)

dave_59
dave_59

Reputation: 42698

Interfaces get compiled just like modules—just once and in any order. Packages must be compiled before they can be imported. Virtual interface references are the one exception with use in packages that you don't have to compile the interface.

You should set up your compile so that everything only gets compiled once. And the only exception to that rule is macro definition files. You can `include them where needed as long as you put compile guards around them. By try to limit that as it still needs to parse the entire file for every include.

Upvotes: 2

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