CODEWITHSUNDEEP
vhdl
devdev
devdev

Reputation: 55

"case statement does not cover all choices. 'others' clause is needed" with std_logic_vector, but I thought all states are defined

signal next_state, current_state: std_logic_vector(2 downto 0) := "000";
begin
myLogic: process(start, reset, current_state)
begin

case current_state is

    when "000" => --code
    --some if statement
        if start = '1' then
            next_state <= "001";
        end if;
    when "001" => 
        --setting signals
    when "010" =>
        --setting signals
    when "011" =>
        --setting signals

    when "100" =>
        --setting signals
    when "101" =>
        --setting signals
    when "110" =>
        --setting signals
    when "111" =>
        --setting stuff
        end case;
        if reset= '1' then 
            current_state <= "000";
        end if;
end process myLogic;

The code I posted above has a state defined by a 3 bit logic vector. But the error I get is that not all cases are covered. When I put a case others statement, my code always goes into others case.

Upvotes: 1

Views: 3067

Answers (1)

snus74
snus74

Reputation: 451

You have to cover all possible cases. Logic signals can have any value in this list: 'U', 'X', '0', ' 1', 'Z', 'W', 'L', 'H'. Since in your case all values different from '0' and '1' are irrelevant, you should add a default case in your switch (in case something wrong happens, and the condition signal has a different value than expected for example)

when others =>

Upvotes: 1

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