xilinix vivado: infer FREQ_HZ using a Verilog/VHDL attribute tag

Question

let's say i'm using xilinx Vivado, with the following verilog code, that I insert into a block design using insert module:

module vivado_amm_ip #(
   parameter lw = 8,
   parameter aw = 32,
   parameter dw = 64
) ( 
    // Avalon Master
    /*Synchrnous Reset Output To Avalon                                   */            
    output wire                m_amm_aresetn,   

    /* Clock Output To Avalon ............................................*/            
    output wire                m_amm_aclk,

    (* X_INTERFACE_INFO = "xilinx.com:interface:avalon:1.0 m_amm ADDRESS" *)            
    output reg  [aw-1:0]       m_amm_addr,      

    (* X_INTERFACE_INFO = "xilinx.com:interface:avalon:1.0 m_amm WRITE" *)              
    output reg                 m_amm_wen,   

    (* X_INTERFACE_INFO = "xilinx.com:interface:avalon:1.0 m_amm WRITEDATA" *)          
    output reg  [dw-1:0]       m_amm_wdata,

    (* X_INTERFACE_INFO = "xilinx.com:interface:avalon:1.0 m_amm WAITREQUEST" *)        
    input  wire                m_amm_wait,   //unused 

    (* X_INTERFACE_INFO = "xilinx.com:interface:avalon:1.0 m_amm READ" *)               
    output wire                m_amm_ren,    //unused

    (* X_INTERFACE_INFO = "xilinx.com:interface:avalon:1.0 m_amm READDATA" *)           
    input  wire [dw-1:0]       m_amm_rdata,     

    (* X_INTERFACE_INFO = "xilinx.com:interface:avalon:1.0 m_amm READDATAVALID" *)      
    input  wire                m_amm_rvalid,    

    (* X_INTERFACE_INFO = "xilinx.com:interface:avalon:1.0 m_amm BEGINBURSTTRANSFER" *) 
    output wire                m_amm_bstart, //unused
    
    (* X_INTERFACE_INFO = "xilinx.com:interface:avalon:1.0 m_amm BURSTCOUNT" *)         
    output wire [lw-1:0]       m_amm_bcount, //unused       
);

endmodule

When I reload the design into vivado, i always get the following error message:

[IP_Flow 19-4751] Bus Interface 'm_amm_aclk': FREQ_HZ bus parameter is missing for output clock interface.

How to get rid of the infamous Vivado FREQ_HZ missing error when infering an amm avalon bus port in verilog?

There should be some type of attribute tag that I put into the Module above the amm clock signal? no?

However, I can find that in Vivado's documentation anywhere on how to add this attribution for an amm port...

Answer 1

based on EML's answer:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity vivado_amm_core is
    port (
        s_amm_aclk           :in  std_logic;
        s_amm_aresetn        :in  std_logic;        
        s_amm_wait           :out std_logic; 
        s_amm_bstart         :in  std_logic;
        s_amm_bcount         :in  std_logic_vector(m_axi_lw-1 downto 0);        
        s_amm_blast          :in  std_logic;
        s_amm_addr           :in  std_logic_vector(m_axi_aw-1 downto 0);
        s_amm_ren            :in  std_logic;
        s_amm_rdata          :out std_logic_vector(m_axi_dw-1 downto 0);
        s_amm_rvalid         :out std_logic;
        s_amm_wen            :in  std_logic; 
        s_amm_wdata          :in  std_logic_vector(m_axi_dw-1 downto 0);
    );
end entity;

architecture rtl of amm_core is

  -- X_INTERFACE_INFO Attribute only works in ghdl if compiled as 
  --    "ghdl.exe -a -frelaxed-rules --std=08 --ieee=synopsys ..."     
  
  -- only need this declaration once per multiple interfaces...
  ATTRIBUTE X_INTERFACE_INFO      :STRING;  
  ATTRIBUTE X_INTERFACE_PARAMETER :STRING;
        
  attribute X_INTERFACE_INFO      of s_amm_aclk       :signal is "xilinx.com:signal:clock:1.0 s_amm_clk      CLK";
  attribute X_INTERFACE_INFO      of s_amm_aresetn    :signal is "xilinx.com:signal:clock:1.0 s_amm_aresetn  RST";  
  ATTRIBUTE X_INTERFACE_PARAMETER of s_amm_aclk       :SIGNAL is "ASSOCIATED_BUSIF s_amm, ASSOCIATED_RESET s_amm_aresetn, FREQ_HZ 100000000";                              
  attribute X_INTERFACE_INFO      of s_amm_wait       :signal is "xilinx.com:interface:avalon:1.0 s_amm WAITREQUEST";
  attribute X_INTERFACE_INFO      of s_amm_addr       :signal is "xilinx.com:interface:avalon:1.0 s_amm ADDRESS";
  attribute X_INTERFACE_INFO      of s_amm_ren        :signal is "xilinx.com:interface:avalon:1.0 s_amm READ";  
  attribute X_INTERFACE_INFO      of s_amm_rdata      :signal is "xilinx.com:interface:avalon:1.0 s_amm READDATA";
  attribute X_INTERFACE_INFO      of s_amm_rvalid     :signal is "xilinx.com:interface:avalon:1.0 s_amm READDATAVALID";
  attribute X_INTERFACE_INFO      of s_amm_wen        :signal is "xilinx.com:interface:avalon:1.0 s_amm WRITE";
  attribute X_INTERFACE_INFO      of s_amm_wdata      :signal is "xilinx.com:interface:avalon:1.0 s_amm WRITEDATA";
  attribute X_INTERFACE_INFO      of s_amm_bstart     :signal is "xilinx.com:interface:avalon:1.0 s_amm BEGINBURSTTRANSFER";
  attribute X_INTERFACE_INFO      of s_amm_bcount     :signal is "xilinx.com:interface:avalon:1.0 s_amm BURSTCOUNT";

begin

end architecuture;

Answer 2

module bd_axicore_pcie(
        
    //====================================================================
     // Verilo-2001 MACROS to Define Vivado Block Design Interfaces
    //====================================================================
    // PCIe Core Clock
    `define hz_pcie  62500000       
    
    // ZYNQ Fast Clock
    `define  hz_sys  50000000       
    
    //(NOTE: no spaces allowed after backslash lines continuation)

    // INPUT CLOCK, with inteface
    `define k(name_clock, name_reset, name_interface) \
        (* X_INTERFACE_INFO = `"xilinx.com:signal:clock:1.0 name_clock CLK`" *) \
        (* X_INTERFACE_PARAMETER = `"XIL_INTERFACENAME name_clock,  ASSOCIATED_BUSIF name_interface, ASSOCIATED_RESET name_reset `" *)

    // OUTPUT CLOCK, with interface
    `define c(name_clock, name_reset, freq_hz, name_interface) \
        (* X_INTERFACE_INFO = `"xilinx.com:signal:clock:1.0 name_clock CLK`" *) \
        (* X_INTERFACE_PARAMETER = `"XIL_INTERFACENAME name_clock,  ASSOCIATED_BUSIF name_interface, ASSOCIATED_RESET name_reset, FREQ_HZ freq_hz `" *)

    // OUTPUT CLOCK, no Interface
    `define z(name_clock, name_reset, freq_hz) \
        (* X_INTERFACE_INFO = `"xilinx.com:signal:clock:1.0 name_clock CLK`" *) \
        (* X_INTERFACE_PARAMETER = `"ASSOCIATED_RESET name_reset, FREQ_HZ freq_hz `" *)

    // INPUT CLOCK, no Interface
    `define v(name_clock, name_reset) \
        (* X_INTERFACE_INFO = `"xilinx.com:signal:clock:1.0 name_clock CLK`" *) \
        (* X_INTERFACE_PARAMETER = `"ASSOCIATED_RESET name_reset `" *)

    // map signal as interface reset
    `define r(name_reset) \
        (* X_INTERFACE_INFO = `"xilinx.com:signal:reset:1.0 name_reset RST `" *) \
        (* X_INTERFACE_PARAMETER = `"POLARITY ACTIVE_LOW`" *)

    // map signal to interface
    `define x(name_iterface, name_item) \
        (* X_INTERFACE_INFO = `"xilinx.com:interface:aximm:1.0 name_iterface name_item `" *)


    // map signal to interface
    `define y(name_iterface, name_item) \
        (* X_INTERFACE_INFO = `"xilinx.com:interface:avalon:1.0 name_iterface name_item `" *)

    //====================================================================
    // ZYNQ Fast Clock
    //====================================================================
    input   wire                   fclk_clk,
    output  wire                   fclk_rstn,

    //====================================================================
    // FPGA IO
    //====================================================================
        
    // LED's 
    output  wire [2:0]             pad_led_row,

    // Video In
    input   wire                   pad_vin_clk,
    input   wire                   pad_vin_hs,
    input   wire                   pad_vin_vs,
    input   wire  [23:0]           pad_vin_rgb, 

    // Testbench Signals
    output  wire                   pad_vidbuf_enabled,
    output  wire [7:0]             pad_vidbuf_mode,

    // I2C for PizoZed Board
    inout   wire                   pad_brd_scl,
    inout   wire                   pad_brd_sda,

    //====================================================================
    // PCIE: Clock / reset
    //====================================================================  
    input   wire                   i_pcie_core_linkup,      
    
    //====================================================================
    // PCIE: Status
    //====================================================================
    input   wire                   i_pcie_interrupt,
    output  wire                   o_pcie_stat_configured, 
    output  wire                   o_pcie_stat_linkup, 
    
    //=================================================================================
    // ARTIX AVALON PORT
    //=================================================================================
    `y(s_amm_atx, WAITREQUEST)      output  wire            s_amm_atx_wait,
    `y(s_amm_atx, ADDRESS)          input   wire [31:0]     s_amm_atx_addr,
    `y(s_amm_atx, WRITE)            input   wire            s_amm_atx_wen,   
    `y(s_amm_atx, WRITEDATA)        input   wire [31:0]     s_amm_atx_wdata,
    `y(s_amm_atx, READ)             input   wire            s_amm_atx_ren,     
    `y(s_amm_atx, READDATA)         output  wire [31:0]     s_amm_atx_rdata,
    `y(s_amm_atx, READDATAVALID)    output  wire            s_amm_atx_rvalid,
        
    //=================================================================================
    // "Zynq General Purpose" Bus (AXI-LITE)
    //=================================================================================
    `x(s_axi_zgp, AWADDR)           input   wire [31:0]     s_axi_zgp_awaddr,   
    `x(s_axi_zgp, AWPROT)           input   wire [2:0]      s_axi_zgp_awprot,   
    `x(s_axi_zgp, AWVALID)          input   wire            s_axi_zgp_awvalid,  
    `x(s_axi_zgp, AWREADY)          output  wire            s_axi_zgp_awready,  
    `x(s_axi_zgp, WDATA)            input   wire [31:0]     s_axi_zgp_wdata,   
    `x(s_axi_zgp, WVALID)           input   wire            s_axi_zgp_wvalid,  
    `x(s_axi_zgp, WREADY)           output  wire            s_axi_zgp_wready,  
    `x(s_axi_zgp, WSTRB)            input   wire [3:0]      s_axi_zgp_wstrb,   
    `x(s_axi_zgp, BRESP)            output  wire [1:0]      s_axi_zgp_bresp,   
    `x(s_axi_zgp, WVALID)           output  wire            s_axi_zgp_bvalid,  
    `x(s_axi_zgp, BREADY)           input   wire            s_axi_zgp_bready,  
    `x(s_axi_zgp, ARADDR)           input   wire [31:0]     s_axi_zgp_araddr,   
    `x(s_axi_zgp, ARPROT)           input   wire [2:0]      s_axi_zgp_arprot,   
    `x(s_axi_zgp, ARVALID)          input   wire            s_axi_zgp_arvalid,  
    `x(s_axi_zgp, ARREADY)          output  wire            s_axi_zgp_arready,  
    `x(s_axi_zgp, RDATA)            output  wire [31:0]     s_axi_zgp_rdata,   
    `x(s_axi_zgp, RRESP)            output  wire [1:0]      s_axi_zgp_rresp,   
    `x(s_axi_zgp, RVALID)           output  wire            s_axi_zgp_rvalid,  
    `x(s_axi_zgp, RREADY)           input   wire            s_axi_zgp_rready,


    //=================================================================================
    // PCIE: CTL
    //=================================================================================
    `x(m_axi_pcie_ctl, ARADDR)      output  wire  [31:0]    m_axi_pcie_ctl_araddr,
    `x(m_axi_pcie_ctl, ARREADY)     input   wire            m_axi_pcie_ctl_arready,
    `x(m_axi_pcie_ctl, ARVALID)     output  wire            m_axi_pcie_ctl_arvalid,
    `x(m_axi_pcie_ctl, AWADDR)      output  wire  [31:0]    m_axi_pcie_ctl_awaddr,
    `x(m_axi_pcie_ctl, AWREADY)     input   wire            m_axi_pcie_ctl_awready,
    `x(m_axi_pcie_ctl, AWVALID)     output  wire            m_axi_pcie_ctl_awvalid,
    `x(m_axi_pcie_ctl, BREADY)      output  wire            m_axi_pcie_ctl_bready,
    `x(m_axi_pcie_ctl, BRESP)       input   wire  [1:0]     m_axi_pcie_ctl_bresp,
    `x(m_axi_pcie_ctl, BVALID)      input   wire            m_axi_pcie_ctl_bvalid,
    `x(m_axi_pcie_ctl, RDATA)       input   wire  [31:0]    m_axi_pcie_ctl_rdata,
    `x(m_axi_pcie_ctl, RREADY)      output  wire            m_axi_pcie_ctl_rready,
    `x(m_axi_pcie_ctl, RRESP)       input   wire  [1:0]     m_axi_pcie_ctl_rresp,
    `x(m_axi_pcie_ctl, RVALID)      input   wire            m_axi_pcie_ctl_rvalid,
    `x(m_axi_pcie_ctl, WDATA)       output  wire  [31:0]    m_axi_pcie_ctl_wdata,
    `x(m_axi_pcie_ctl, WREADY)      input   wire            m_axi_pcie_ctl_wready,
    `x(m_axi_pcie_ctl, WSTRB)       output  wire  [3:0]     m_axi_pcie_ctl_wstrb,
    `x(m_axi_pcie_ctl, WVALID)      output  wire            m_axi_pcie_ctl_wvalid,

    //=================================================================================
    // PCIE: DT0
    //=================================================================================
    `x(m_axi_pcie_dt0, ARADDR)    output  wire  [31:0]      m_axi_pcie_dt0_araddr,
    `x(m_axi_pcie_dt0, ARBURST)   output  wire  [1:0]       m_axi_pcie_dt0_arburst,
    `x(m_axi_pcie_dt0, ARID)      output  wire  [3:0]       m_axi_pcie_dt0_arid,
    `x(m_axi_pcie_dt0, ARLEN)     output  wire  [7:0]       m_axi_pcie_dt0_arlen,
    `x(m_axi_pcie_dt0, ARREADY)   input   wire              m_axi_pcie_dt0_arready,
    `x(m_axi_pcie_dt0, ARREGION)  output  wire  [3:0]       m_axi_pcie_dt0_arregion,
    `x(m_axi_pcie_dt0, ARSIZE)    output  wire  [2:0]       m_axi_pcie_dt0_arsize,
    `x(m_axi_pcie_dt0, ARVALID)   output  wire              m_axi_pcie_dt0_arvalid,
    `x(m_axi_pcie_dt0, AWADDR)    output  wire  [31:0]      m_axi_pcie_dt0_awaddr,
    `x(m_axi_pcie_dt0, AWBURST)   output  wire  [1:0]       m_axi_pcie_dt0_awburst,
    `x(m_axi_pcie_dt0, AWID)      output  wire  [3:0]       m_axi_pcie_dt0_awid,
    `x(m_axi_pcie_dt0, AWLEN)     output  wire  [7:0]       m_axi_pcie_dt0_awlen,
    `x(m_axi_pcie_dt0, AWREADY)   input   wire              m_axi_pcie_dt0_awready,
    `x(m_axi_pcie_dt0, AWREGION)  output  wire  [3:0]       m_axi_pcie_dt0_awregion,
    `x(m_axi_pcie_dt0, AWSIZE)    output  wire  [2:0]       m_axi_pcie_dt0_awsize,
    `x(m_axi_pcie_dt0, AWVALID)   output  wire              m_axi_pcie_dt0_awvalid,
    `x(m_axi_pcie_dt0, BID)       input   wire  [3:0]       m_axi_pcie_dt0_bid,
    `x(m_axi_pcie_dt0, BREADY)    output  wire              m_axi_pcie_dt0_bready,
    `x(m_axi_pcie_dt0, BRESP)     input   wire  [1:0]       m_axi_pcie_dt0_bresp,
    `x(m_axi_pcie_dt0, BVALID)    input   wire              m_axi_pcie_dt0_bvalid,
    `x(m_axi_pcie_dt0, RDATA)     input   wire  [63:0]      m_axi_pcie_dt0_rdata,
    `x(m_axi_pcie_dt0, RID)       input   wire  [3:0]       m_axi_pcie_dt0_rid,
    `x(m_axi_pcie_dt0, RLAST)     input   wire              m_axi_pcie_dt0_rlast,
    `x(m_axi_pcie_dt0, RREADY)    output  wire              m_axi_pcie_dt0_rready,
    `x(m_axi_pcie_dt0, RRESP)     input   wire  [1:0]       m_axi_pcie_dt0_rresp,
    `x(m_axi_pcie_dt0, RVALID)    input   wire              m_axi_pcie_dt0_rvalid,
    `x(m_axi_pcie_dt0, WDATA)     output  wire  [63:0]      m_axi_pcie_dt0_wdata,
    `x(m_axi_pcie_dt0, WLAST)     output  wire              m_axi_pcie_dt0_wlast,
    `x(m_axi_pcie_dt0, WREADY)    input   wire              m_axi_pcie_dt0_wready,
    `x(m_axi_pcie_dt0, WSTRB)     output  wire  [7:0]       m_axi_pcie_dt0_wstrb,
    `x(m_axi_pcie_dt0, WVALID)    output  wire              m_axi_pcie_dt0_wvalid,


    //=================================================================================
    // PCIE: DT1
    //=================================================================================
    `x(s_axi_pcie_dt1, ARADDR)    input   wire  [31:0]      s_axi_pcie_dt1_araddr,
    `x(s_axi_pcie_dt1, ARBURST)   input   wire  [1:0]       s_axi_pcie_dt1_arburst,
    `x(s_axi_pcie_dt1, ARCACHE)   input   wire  [3:0]       s_axi_pcie_dt1_arcache,
    `x(s_axi_pcie_dt1, ARLEN)     input   wire  [7:0]       s_axi_pcie_dt1_arlen,
    `x(s_axi_pcie_dt1, ARLOCK)    input   wire              s_axi_pcie_dt1_arlock,
    `x(s_axi_pcie_dt1, ARPROT)    input   wire  [2:0]       s_axi_pcie_dt1_arprot,
    `x(s_axi_pcie_dt1, ARREADY)   output  wire              s_axi_pcie_dt1_arready,
    `x(s_axi_pcie_dt1, ARSIZE)    input   wire  [2:0]       s_axi_pcie_dt1_arsize,
    `x(s_axi_pcie_dt1, ARVALID)   input   wire              s_axi_pcie_dt1_arvalid,
    `x(s_axi_pcie_dt1, AWADDR)    input   wire  [31:0]      s_axi_pcie_dt1_awaddr,
    `x(s_axi_pcie_dt1, AWBURST)   input   wire  [1:0]       s_axi_pcie_dt1_awburst,
    `x(s_axi_pcie_dt1, AWCACHE)   input   wire  [3:0]       s_axi_pcie_dt1_awcache,
    `x(s_axi_pcie_dt1, AWLEN)     input   wire  [7:0]       s_axi_pcie_dt1_awlen,
    `x(s_axi_pcie_dt1, AWLOCK)    input   wire              s_axi_pcie_dt1_awlock,
    `x(s_axi_pcie_dt1, AWPROT)    input   wire  [2:0]       s_axi_pcie_dt1_awprot,
    `x(s_axi_pcie_dt1, AWREADY)   output  wire              s_axi_pcie_dt1_awready,
    `x(s_axi_pcie_dt1, AWSIZE)    inout   wire  [2:0]       s_axi_pcie_dt1_awsize,
    `x(s_axi_pcie_dt1, AWVALID)   input   wire              s_axi_pcie_dt1_awvalid,
    `x(s_axi_pcie_dt1, BREADY)    input   wire              s_axi_pcie_dt1_bready,
    `x(s_axi_pcie_dt1, BRESP)     output  wire  [1:0]       s_axi_pcie_dt1_bresp,
    `x(s_axi_pcie_dt1, BVALID)    output  wire              s_axi_pcie_dt1_bvalid,
    `x(s_axi_pcie_dt1, RDATA)     output  wire  [63:0]      s_axi_pcie_dt1_rdata,
    `x(s_axi_pcie_dt1, RLAST)     output  wire              s_axi_pcie_dt1_rlast,
    `x(s_axi_pcie_dt1, RREADY)    input   wire              s_axi_pcie_dt1_rready,
    `x(s_axi_pcie_dt1, RRESP)     output  wire  [1:0]       s_axi_pcie_dt1_rresp,
    `x(s_axi_pcie_dt1, RVALID)    output  wire              s_axi_pcie_dt1_rvalid,
    `x(s_axi_pcie_dt1, WDATA)     input   wire  [63:0]      s_axi_pcie_dt1_wdata,
    `x(s_axi_pcie_dt1, WLAST)     input   wire              s_axi_pcie_dt1_wlast,
    `x(s_axi_pcie_dt1, WREADY)    output  wire              s_axi_pcie_dt1_wready,
    `x(s_axi_pcie_dt1, WSTRB)     input   wire  [7:0]       s_axi_pcie_dt1_wstrb,
    `x(s_axi_pcie_dt1, WVALID)    input   wire              s_axi_pcie_dt1_wvalid,

    //=================================================================================
    // Clocks & Resets
    //=================================================================================

    `r(s_axi_zgp_rstn)   output  wire  s_axi_zgp_rstn,
    `r(s_amm_atx_rstn)   output  wire  s_amm_atx_rstn,  
    `r(i_pcie_core_rstn) input   wire  i_pcie_core_rstn,                

    `define buses   m_axi_pcie_dt0:s_axi_pcie_dt1:m_axi_pcie_ctl

    `c(s_axi_zgp_clk,    s_axi_zgp_rstn,   `hz_sys,  s_axi_zgp) output  wire    s_axi_zgp_clk,
    `c(s_amm_atx_clk,    s_amm_atx_rstn,   `hz_sys,  s_amm_atx) output  wire    s_amm_atx_clk,
    `k(i_pcie_core_clk,  i_pcie_core_rstn,           `buses)    input   wire    i_pcie_core_clk         
    
    `undef buses
    `undef k
    `undef c
    `undef z
    `undef v
    `undef r
    `undef x
    `undef y    
    `undef hz_pcie
    `undef hz_sys   
);