CODEWITHSUNDEEP
verilogvivado
ProgrammingGuy
ProgrammingGuy

Reputation: 41

Passing parameters between modules in Verilog

I am trying to learn how to pass parameters in Verilog. So far I've learned that the declaration looks like this:

module funct #(parameter n = 32)
(input clk, input [n-1:0]in, input reset, input L,
input load, input shift, output reg[n-1:0] out);

I instantiate another module within that module that depends on the parameter, so I defined the parameter there as well.

module funct2 #(parameter n = 32) (
    input clk,
    input [n-1:0] in,
    input rst,
    input  L,
    output  [n-1:0] out
    );

My question is how to call funct2 within funct?

I was also wondering how I can instantiate funct within the testbench folder. Without the parameter, it looked like this

funct uut(.clk(clk),.in(in), .reset(reset),.L(L), .load(load), .shift(shift), .out(out));

Upvotes: 1

Views: 1101

Answers (1)

toolic
toolic

Reputation: 62096

The following syntax is used to instantiate funct2 within funct, passing the parameter into the module:

funct2 #(.n(n)) i1 (.clk(clk), .in(in), .rst(reset), .L(L), .out(out));

Refer to IEEE Std 1800-2017, section 23.3.2 Module instantiation syntax.

The syntax you used to instantiate funct inside the testbench is valid, as you've discovered. The default value of 32 is used in this case. Optionally, you could use the #(.n(n)) syntax to explicitly show that you are passing a parameter.

Upvotes: 1

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