shubham737
shubham737

Reputation: 37

Why does ModelSim simulation freeze?

This is the Verilog code for '10101' non overlapping sequence detector. When I compile this code, it doesn't show any error. But, when I simulate the code, ModelSim stops working and freezes indefinitely. I cant find the error or where the problem is.

module seq_det(y,x,clk,rst);
output reg y;
input x,clk,rst;

reg[2:0] pr_st,nx_st;

parameter s0=3'b000;
parameter s1=3'b001;
parameter s2=3'b010;
parameter s3=3'b011;
parameter s4=3'b100;

always {y,nx_st}= fsm(x,pr_st);
always @(posedge clk)
    begin if(rst)begin
            y=0;
            nx_st=s0;
            end
          else nx_st=pr_st;
    end

//function defined here
function [3:0] fsm;
input sm_x;
input sm_ps;

reg sm_y;
reg[2:0] sm_ns;

begin
case(sm_ps)
s0:begin
    if(sm_x==0) begin
    sm_y=0;
    sm_ns=s0;
    end
    else begin
    sm_y=0;
    sm_ns=s1;
    end
   end
s1:begin
    if(sm_x==1) begin
    sm_y=0;
    sm_ns=s1;
    end
    else begin
    sm_y=0;
    sm_ns=s2;
    end
   end
s2:begin
    if(sm_x==0) begin
    sm_y=0;
    sm_ns=s0;
    end
    else begin
    sm_y=0;
    sm_ns=s3;
    end
   end
s3:begin
    if(sm_x==1) begin
    sm_y=0;
    sm_ns=s1;
    end
    else begin
    sm_y=0;
    sm_ns=s4;
    end
   end
s4:begin
    sm_y=sm_x;
    sm_ns=s0;
   end
endcase
fsm={sm_y,sm_ns};
end
endfunction
endmodule

Upvotes: 1

Views: 820

Answers (1)

toolic
toolic

Reputation: 62236

When I run your code with VCS, I get this message:

Warning-[PALF] Potential always loop found This always block has no event control or delay statements, it might cause an infinite loop in simulation.

It points to this line in your code:

always {y,nx_st}= fsm(x,pr_st);

The message disappears when I change it to this:

always @* {y,nx_st}= fsm(x,pr_st);

@* is an implicit sensitivity list. The always block will now only be triggered whenever x or pr_st changes value.


Note: you can also try your code on other simulators on edaplayground.

Upvotes: 1

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