CODEWITHSUNDEEP
system-verilog
Bimo
Bimo

Reputation: 6647

systemverilog name conflict between imported packages

As you can see in code below I have the same parameter name in both package files and the compiler fails due to this ambiguity. How to fix the SystemVerilog code in the case below?

//--------------------------------------
package register1_pkg;

    parameter base_core_regs    = 32'h00003000;

    parameter addr_testreg         = (base_axicore_regs + 32'h0000000C);

endpackage

//--------------------------------------
package register2_pkg;

    parameter base_user_regs    = 32'h00007000;

    parameter addr_testreg         = (base_user_regs + 32'h00000014);

endpackage

//--------------------------------------
module testbench();

timeunit 1ns/10ps; 

import register1_pkg::*;
import register2_pkg::*;

task write;
   input integer addr;
   input integer data;
begin
   $display("write  addr:%x data:%x", addr, data);
end
endtask;

initial begin
    write(addr_testreg, 32'hABCD1234);

    $stop;
end

endmodule

Upvotes: 0

Views: 1804

Answers (2)

dave_59
dave_59

Reputation: 42748

You cannot use the wildcard import ::* when you have multiple packages with the same symbol name you want to import. You need to explicitly reference the package symbol to remove the ambiguity.

You can either do an explicit import:

import register1_pkg::addr_testreg;

or you can explicitly reference the symbol without importing it

write(register1_pkg::addr_testreg, 32'hABCD1234);

Upvotes: 1

Matthew
Matthew

Reputation: 13987

Just delete your import statements and do this instead:

write(register1_pkg::addr_testreg, 32'hABCD1234);
write(register2_pkg::addr_testreg, 32'hABCD1234);

https://www.edaplayground.com/x/Kpfe

//--------------------------------------
package register1_pkg;

    parameter base_core_regs    = 32'h00003000;

    parameter addr_testreg         = (base_core_regs + 32'h0000000C);

endpackage

//--------------------------------------
package register2_pkg;

    parameter base_user_regs    = 32'h00007000;

    parameter addr_testreg         = (base_user_regs + 32'h00000014);

endpackage

//--------------------------------------
module testbench();

timeunit 1ns/10ps; 

task write;
   input integer addr;
   input integer data;
begin
   $display("write  addr:%x data:%x", addr, data);
end
endtask;

initial begin
  write(register1_pkg::addr_testreg, 32'hABCD1234);
  write(register2_pkg::addr_testreg, 32'hABCD1234);
  $stop;
end

endmodule

Upvotes: 1

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