CODEWITHSUNDEEP
verilog
eliesmith
eliesmith

Reputation: 59

Verilog program is not terminating

I am trying to create a four element direct mapped cache with 4-bit memory address. After creating a cache, I am reading the values from the file to figure out hits or misses on cache. But, somehow, my program is not terminating. Can someone please help me with this? I expect the simulation to end when the program has read the file. Here is the code with the testbench.

module cache_memory_direct_mapped(input clk,
                        input reset,
                        input [3:0]read_addr,
                        output reg hit,
                        output reg miss);
 reg [1:0]c1[3:0];
 reg [7:0]hit_count =8'h00; 
 reg [7:0]miss_count = 8'h00; 
        
always @(posedge clk, posedge reset)                        
 begin
   if(reset)
      begin
       c1[0] <= 2'hx;
       c1[1] <= 2'hx;
       c1[2] <= 2'hx;
       c1[3] <= 2'hx;
      end   
    else  
 begin
  if(read_addr[3:2] == c1[0])
  //if(read_addr[3:2] == c1[0] || read_addr[3:2] == c1[1] || read_addr[3:2] == c1[2] || 
//read_addr[3:2] == c1[3])
  begin
   hit <= 1;
   hit_count <= hit_count + 1;
   miss <= 0;
   end
else
 begin
   hit <= 0;
   miss <= 1;
   miss_count <= miss_count + 1;
    if(read_addr[1:0] == 0 )
      c1[0] <= read_addr[3:2];
    else if(read_addr[1:0] == 1 )
      c1[1] <= read_addr[3:2];  
    else if(read_addr[1:0] == 2 )
      c1[2] <= read_addr[3:2];        
    else if(read_addr[1:0] == 3 )
      c1[3] <= read_addr[3:2];  
     end
     end
     end
     endmodule


module Tb_direct_mapped;

// Inputs
reg clk;
reg reset;
reg [3:0] read_addr;

// Outputs
wire hit;
wire miss;

integer data_file ; // file handler
integer scan_file ; // file handler
reg [4:0]captured_data;

// Instantiate the Unit Under Test (UUT)
cache_memory_direct_mapped uut (
    .clk(clk), 
    .reset(reset), 
    .read_addr(read_addr), 
    .hit(hit), 
    .miss(miss)
);

initial begin
    // Initialize Inputs
    clk = 0;
    reset = 0;
    data_file = $fopen("data_file.txt", "r");
end

always
#10 clk= ~clk;


always @(posedge clk) begin
scan_file = $fscanf(data_file, "%h\n", captured_data);
if (!$feof(data_file)) begin
 read_addr <= captured_data;
 end
 end

  
 endmodule

Upvotes: 1

Views: 304

Answers (1)

toolic
toolic

Reputation: 62236

The simulation does not terminate because you did not specify when it should end.

always
#10 clk= ~clk;

The code above instructs the simulator to add a new event every 10 time units. It continues to add new events indefinitely, which is why the simulation does not end. One common way to stop a simulation is to use the $finish system task:

initial #100 $finish;

You should change 100 to be something more meaningful to your testbench.

Or, if you want to end the simulation after the file is read:

always @(posedge clk) begin
    scan_file = $fscanf(data_file, "%h\n", captured_data);
    if (!$feof(data_file)) begin
        read_addr <= captured_data;
    end else begin
        $finish;
    end
end

Upvotes: 1

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