CODEWITHSUNDEEP
verilogmodelsim
Programming Learner
Programming Learner

Reputation: 11

Port size (12 or 12) does not match connection size (6)

Booth algorithm is a multiplication operation that multiplies two numbers in two complement notation

The Booth multiplier has been widely used for high performance signed multiplication by encoding and thereby reducing the number of partial products

May I know how to modify my Verilog coding as below because get the error message:

Port size (12 or 12) does not match connection size (6)

module alu(out, in1, in2);

input [5:0] in1;
input [5:0] in2;
output [11:0] out;

assign out = in1 + in2; 

endmodule

module booth(out, in1, in2, clk, start);

parameter width = 6;
input clk, start;
input [5:0] in1;            //multiplicand
input [5:0] in2;            //multiplier
output [11:0] out;          //product

reg [5:0] A, Q, M;
reg Q_1; 
reg count;

wire[5:0] sum, difference;

always @(posedge clk)
begin
  if (start) begin
  A <= 6'b0;
  M <= in1;
  Q <= in2;    
  Q_1 <= 1'b0;
  count <= 2'b0;
end
else begin
  case ({Q[0], Q_1})
    2'b0_1: {A, Q, Q_1} <= {sum[5], sum, Q};
    2'b1_0: {A, Q, Q_1} <= {difference[5], difference, Q};
    default: {A, Q, Q_1} <= {A[5], A, Q};
    endcase
    count <= count + 1'b1;
end
end

alu adder (sum, A, M);
alu subtracter (difference, A, ~M);

assign out = {A, Q};

endmodule


`timescale 1ns / 10ps
`define CYCLE 30

  module booth_tb;
  parameter width = 6;
  
  wire [2*width-1:0] out;
  reg [width-1:0] in1;
  reg [width-1:0] in2;
  reg clk, start;
  
  integer num = 1;
  integer i;
  integer j;
  integer ans;
  integer err = 0;
  
  booth booth(.out(out), .in1(in1), .in2(in2), .clk, .start);
  
  initial begin
    for(i = (-(1<<width-1)+1); i < (1<<width-1); i = i+1) begin
      for(j = (-(1<<width-1)); j < (1<<width-1); j = j+1) begin
        in1 = i[width-1:0];
        in2 = j[width-1:0];
        #`CYCLE;
        ans = i * j;
        if(out == ans[2*width-1:0])
          $display("%d data is correct", num);
        else begin
          $display("%d data is error %b, correct is %b", num, out, ans[2*width-1:0]);
          err = err + 1;
        end
        num = num + 1;
      end
    end
    
    if(err == 0) begin
      $display("-------------------PASS-------------------");
      $display("All data have been generated successfully!");    
    end else begin
      $display("-------------------ERROR-------------------");
      $display("There are %d errors!", err);
    end
    
    #10 $finish;
  end 
endmodule

Upvotes: 1

Views: 812

Answers (1)

toolic
toolic

Reputation: 62236

If that was your exact error message, then it was not very specific. You can try your code on other simulators if you sign up for a free account on edaplayground. You might get more specific messages.

When I compile your code with VCS, I get a more helpful message:

Warning-[PCWM-W] Port connection width mismatch
"alu adder(sum, A, M);"
  The following 6-bit expression is connected to 12-bit port "out" of module 
  "alu", instance "adder".
  Expression: sum

This clearly shows your connection mistake. You should only connect signals of the same width together. For example, you could change:

wire[5:0] sum, difference;

to:

wire[11:0] sum, difference;

That gets rid of the compile warnings for me, but you need to decide what the proper width should be for these signals.

Upvotes: 0

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