CODEWITHSUNDEEP
system-veriloguvmsystem-verilog-assertions
Alexandr Bolotnikov
Alexandr Bolotnikov

Reputation: 35

recomend the way to write a monitor in UVM with defferent event polarity

I am trying to implement a monitor for VDU(Video display unit) and the way the VDU can be programmed says that sync signals have controllable polarity. This means than according to VDU settings monitor should react on @posedge or @negedge event. Is there any way to pass the type (means posesge or negedge) via configuration data base or do something like this. Instead of write if(truth) @posedge else @negedge. And assertion also needs to be controlled this way but assertion at list designed to take event type as an argument but I am no sure config data base calls are allowed inside interface.

Upvotes: -1

Views: 841

Answers (2)

Greg
Greg

Reputation: 19112

On option is to conditionally trigger an event. For example, you can have the bellow in you interface:

event mon_clk_ev;
bit   mon_polarity;
always @(posedge clk) if ( mon_polarity) ->mon_clk_ev;
always @(negedge clk) if (!mon_polarity) ->mon_clk_ev;

Then you can use mon_clk_ev are the clock event in your monitor, interface, clocking block, or assertion.

mon_polarity could be assigned by your monitor, uvm_config_db, or other logic.

Example using uvm_config_db (Note using uvm_bitstream_t so it can be assigned with the uvm_set_config_int plusarg):

initial begin
  start_of_simulation_ph.wait_for_state( UVM_PHASE_STARTED, UVM_GTE );
  if (!uvm_config_db#(uvm_bitstream_t)::exists(null,"","mon_polarity")) begin
    // default if not in database
    uvm_config_db#(uvm_bitstream_t)::set(null,"*","mon_polarity",1'b1); 
  end
  forever begin
    void'(uvm_config_db#(uvm_bitstream_t)::get(null,"","mon_polarity",mon_polarity));
    uvm_config_db#(uvm_bitstream_t)::wait_modified(null,"","mon_polarity");
  end
end

Upvotes: 1

dave_59
dave_59

Reputation: 42698

You should write your code assuming positive polarity, but feed them through an xor operator.

logic signal;           // your signal from DUT
logic signal_corrected; // signal with positive polarity
bit signal_polarity;  // 0 = positive ; 1 = negative
assign signal_corrected = signal ^ signal_polarity;

Now you can use signal_corrected in your assertions. You can certainly call uvm_config_db#(bit)::get() from the interface if it has been set in your testbench. You might need to use uvm_config_db#(bit)::wait_modified() to wait for it to be set before you get it.

Upvotes: 1

Related Questions