CODEWITHSUNDEEP
verilog
SooonSooon
SooonSooon

Reputation: 21

Error in ModelSim, near "=": syntax error, unexpected '='. Syntax error found in the scope following 'Y'. Is there a missing '::'?

I'm making the master JK flipflop, and the errors came out like this:

** Error: (vlog-13069) C:/Windows/System32/ssy_1775_final.v(13): near "=": syntax error, unexpected '='.
** Error: C:/Windows/System32/ssy_1775_final.v(13): (vlog-13205) Syntax error found in the scope following 'Y'. Is there a missing '::'?

The code I made is as below:

    module JK_FlipFlop(J, K, clk, Y_BAR, Y, Q);
    input J, K, clk;
    output Y, Q;
    reg Y_BAR;
    wire Y, Q;

always@(posedge clk) 
assign Y_BAR = ~Y;
begin
if(J==0 && K==0) 
begin Y=Y; Y_BAR=Y_BAR; end
else if(J==0 && K==1) 
begin Y<=1'b0; Y_BAR<=1'b1; end
else if(J==1 && K==0) 
begin Y<=1'b1; Y_BAR<=1'b0; end
else if(J==1 && K==1) 
begin Y=Y_BAR; Y_BAR=Y; end
end

always@(negedge clk)
begin
if(Y==0 && Y_BAR==0)
 begin end
else if(Y==0 && Y_BAR==1)
  begin Q<=1'b0; end
else if(Y==1 && Y_BAR==0)
  begin Q<=1'b1; end
else if(Y==1 && Y_BAR==1)
  begin Q<=~Q; end
end

endmodule

I don't know why the error came out.

I pray that someone will spare me.

Upvotes: 2

Views: 2138

Answers (1)

toolic
toolic

Reputation: 62227

You have multiple errors in your port and signal declarations. Since you make procedural assignments to all your outputs, they must all be declared as reg, not wire. To reduce signal name duplication, thereby avoiding common errors like this, use ANSI style ports as shown below.

Another problem is that you should not use the assign keyword inside the always block. The following code compiles without errors:

module JK_FlipFlop (
    input J, K, clk,
    output reg Y, Q, Y_BAR
);

always@(posedge clk) 
begin
    Y_BAR = ~Y;
    if(J==0 && K==0) 
    begin Y=Y; Y_BAR=Y_BAR; end
    else if(J==0 && K==1) 
    begin Y<=1'b0; Y_BAR<=1'b1; end
    else if(J==1 && K==0) 
    begin Y<=1'b1; Y_BAR<=1'b0; end
    else if(J==1 && K==1) 
    begin Y=Y_BAR; Y_BAR=Y; end
end

always@(negedge clk)
begin
    if(Y==0 && Y_BAR==0)
     begin end
    else if(Y==0 && Y_BAR==1)
      begin Q<=1'b0; end
    else if(Y==1 && Y_BAR==0)
      begin Q<=1'b1; end
    else if(Y==1 && Y_BAR==1)
      begin Q<=~Q; end
end

endmodule

Your code would be easier to understand if you improve the indentation.

Upvotes: 1

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