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vhdlverilogvariable-assignmentcycle
Martin Geisse
Martin Geisse

Reputation: 1441

How do Verilog and VHDL handle conflicting assignments after (n+delta) cycles?

To set the stage, assume a circuit that computes ((a AND b) or c), with the inputs a,b,c changing at the same time, e.g. taken from clocked registers. The delay of the AND gate is negligible, and therefore not modeled at all, but the delay of the OR gate is significant, say 5ns.

The gates are modeled by using an operator and a delayed assignment in two separate processes:

Verilog:
    (process 1) temp <= a & b;
    (process 2) out <= #5 temp | c;

VHDL:
    (process 1) temp <= a and b;
    (process 2) out <= temp or c after 5ns;

Now with the right old and new input values, a glitch occurs: (a = 1, b = 1, c = 0) -> (a = 0, b = 1, c = 1). This causes the temp value (output of the AND gate) to become 0 in a delta cycle, and therefore schedule a change of the OR gate to 0 after 5ns. Simultaneously, c becomes 1 and schedules a "change" of the OR gate to 1 (at that time it still is 1).

Now the fun part: Let the inputs change at time 0ns. The change of the OR gate to 1 is scheduled at time 0ns, for time 5ns. The change of the OR gate to 0 is scheduled at time (0ns + 1delta), for 5ns later. A "too simple" model would schedule both for time 5ns and risk that they get executed in the wrong order, leaving the output of the OR gate at 0 erroneously.

The question now is, how do Verilog and VHDL make sure that the glitch gets resolved correctly? Things they could do it that I can imagine:

Please note that I am trying to understand the behaviour prescribed by the two languages, not achieve a specific outcome.

Upvotes: 0

Views: 205

Answers (1)

dave_59
dave_59

Reputation: 42698

For the signal assignments you have shown, Verilog and VHDL both guarantee last write wins. As other have commented, it would have helped to show the complete context of the statements to confirm that is what you intended.

There will be no glitch because the c transition from 0→1 happens before the temp transition from 1→0, separated by a delta cycle. Although you cannot determine the ordering between different concurrent processes, if there is a deterministic ordering within the same process, last write to the same variable wins.

Upvotes: 0

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