CODEWITHSUNDEEP
verilog
marchive7
marchive7

Reputation: 55

verilog Error in If statement. (reg) is not a constant. Target <reg> of concurrent assignment or output port connection should be a net type

I'm making a 8Bit select adder with 4bit adder.

When i try to test this code.

i got a 2 error.

First one is "coutL is not a constant"

Second one is "Target of concurrent assignment or output port

connection should be a net type."

Can anyone help me?

module selectAdd8(
    input [7:0] a,
    input [7:0] b,
    input cin,
    output reg [7:0] sum,
    output reg cout
    );

    reg coutL, sumL, sum0, sum1, cout0, cout1;
    
    always @ (*);

        begin
            
            add4 add_lower(a[3:0],b[3:0],cin,sumL,coutL);
            add4 add4_0(a[7:4],b[7:4],0,sum0,cout0);
            add4 add4_1(a[7:4],b[7:4],1,sum1,cout1);
            
            if (coutL==1) begin
                assign sum = {sum1, sumL};
                assign cout = cout1;
            end else begin
                assign sum = {sum0, sumL};
                assign cout = cout0;
            end
            
        end

endmodule

Upvotes: 0

Views: 475

Answers (1)

Serge
Serge

Reputation: 12354

The following statement makes no sense with semicolon after it:

always @ (*);

I guess the following begin .. end were intended to go with the previous always block. They did not because of the semicolon. In any case, instantiating of modules inside such a block is illegal in verilog, it should be done outside the block and outside of begin/end:

            add4 add_lower(a[3:0],b[3:0],cin,sumL,coutL);
            add4 add4_0(a[7:4],b[7:4],0,sum0,cout0);
            add4 add4_1(a[7:4],b[7:4],1,sum1,cout1);

Both, stand-alone begin/end and if statement represent a generate block in modern verilog. So, the following is a part of the generate block:

            if (coutL==1) begin
                assign sum = {sum1, sumL};
                assign cout = cout1;
            end else begin
                assign sum = {sum0, sumL};
                assign cout = cout0;
            end

But such blocks only operate with constants. So countL must be a constant, i.e. a parameter. It is a reg, therefore, there is an error.

Again, it seems that you intended this as a part of the always block. assign statements within such a block are a very special verilog constructs and should not be used without a very good understanding of what they do.

My guess is that you intended something like the following:

module selectAdd8(
    input [7:0] a,
    input [7:0] b,
    input cin,
    output reg [7:0] sum,
    output reg cout
    );

    reg coutL, sumL, sum0, sum1, cout0, cout1;
    always @ (*)
        begin           
            if (coutL==1) begin
                sum = {sum1, sumL};
                cout = cout1;
            end else begin
                sum = {sum0, sumL};
                cout = cout0;
            end            
        end            
   
    add4 add_lower(a[3:0],b[3:0],cin,sumL,coutL);
    add4 add4_0(a[7:4],b[7:4],0,sum0,cout0);
    add4 add4_1(a[7:4],b[7:4],1,sum1,cout1);
endmodule

Upvotes: 2

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