CODEWITHSUNDEEP
verilogsimulationsystem-verilogmodelsimtest-bench
Ali Eftekhari
Ali Eftekhari

Reputation: 23

Unexpected warning in Verilog simulation for port size

I couldn't figure out why the simulator gives the warning and why the circuit does not work properly.

This is the Verilog code:

`timescale 1ns/1ns
module circuitIVEightBitAssign(input [7:0]a,flag,output [7:0]b);
    assign #(143) b = flag ? ~a : (~(a) + 1'b1) ;
endmodule

and this is the testbench:

`timescale 1ns/1ns
module circuitIVAllTB();
    wire [7:0]b1;
    reg [7:0]a;
    reg flag;
    circuitIVEightBitAssign g2(a,flag,b1);
    initial begin
    #10
    flag = 0;
    a = 8'b00000000;
    #500
    a = 8'b11111111;
    #500
    a = 8'b00000111;
    #500
    flag = 1;
    #500
    flag = 0;
    #500
    $stop;
    end
endmodule

The warning is:

** Warning: (vsim-3015) [PCDPC] - Port size (8) does not match connection size (1) for port 'flag'. The port definition is at: C:/Users/Ali/OneDrive/Desktop/CA2_00FALL/circuitIVEightBitAssign.v(2). Time: 0 ns Iteration: 0 Instance: /circuitIVAllTB/g2 File: C:/Users/Ali/OneDrive/Desktop/CA2_00FALL/circuitIVAllTB.v Line: 6

But, flag is 1-bit. Why does modelsim give me this warning?

Upvotes: 1

Views: 147

Answers (1)

toolic
toolic

Reputation: 62236

In the circuitIVEightBitAssign module, you declared flag as 8-bit, not 1-bit. To declare it as 1-bit, you need to add the input keyword again. Change:

module circuitIVEightBitAssign(input [7:0]a,flag,output [7:0]b);

to:

module circuitIVEightBitAssign(input [7:0]a,input flag,output [7:0]b);

In your code, the width information is used for both signals. input [7:0]a,flag is the same as:

input [7:0] a,
input [7:0] flag,

Upvotes: 0

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