CODEWITHSUNDEEP
verilog
mu9u1t
mu9u1t

Reputation: 55

For instance uut/A1/, width 1 of formal port S is not equal to width 4 of actual signal in1

Can anyone tell why I am getting these warnings?

For instance uut/A1/, width 1 of formal port S is not equal to width 4 of actual signal in1.

For instance uut/A1/, width 1 of formal port Cout is not equal to width 4 of actual signal in2.

For instance uut/A1/, width 1 of formal port A is not equal to width 4 of actual signal s1.

For instance uut/A2/, width 1 of formal port S is not equal to width 4 of actual signal in3.

For instance uut/A2/, width 1 of formal port Cout is not equal to width 4 of actual signal in4.

For instance uut/A2/, width 1 of formal port A is not equal to width 4 of actual signal s2.

module binary(A,B,P);
input [2:0]A;
input [3:0]B;
output [6:0]P;
wire c1,c2;
wire [3:0]s1,in1,in2,in3,in4,s2;

assign in1[0] = A[0] & B[1];
assign in1[1] = A[0] & B[2];
assign in1[2] = A[0] & B[3];

assign in2[0] = A[1] & B[0];
assign in2[1] = A[1] & B[1];
assign in2[2] = A[1] & B[2];
assign in2[3] = A[1] & B[3];

assign in3[0] = A[2] & B[0];
assign in3[1] = A[2] & B[1];
assign in3[2] = A[2] & B[2];
assign in3[3] = A[2] & B[3];

FA A1(in1,in2,s1,c1);
assign in4[0] = s1[1];
assign in4[1] = s1[2];
assign in4[2] = s1[3];
assign in4[3] = c1;

FA A2(in3,in4,s2,c2);
assign P[0] = A[0] & B[0];
assign P[1] = s1[0];
assign P[2] = s2[0];
assign P[3] = s2[1];
assign P[4] = s2[2];
assign P[5] = s2[3];
assign P[6] = c2;

endmodule


module FA(S, Cout, A, B, Cin);
output S;
  output Cout;
  input  A;
  input  B;
  input  Cin;

  wire   w1;
  wire   w2;
  wire   w3;
  wire   w4;

  xor(w1, A, B);
  xor(S, Cin, w1);
  and(w2, A, B);   
  and(w3, A, Cin);
  and(w4, B, Cin);   
  or(Cout, w2, w3, w4);
endmodule

Upvotes: 0

Views: 213

Answers (1)

toolic
toolic

Reputation: 62045

You declared the S output port of the FA module as a 1-bit signal:

module FA(S, Cout, A, B, Cin);
output S;

Inside module binary, you declared in1 as a 4-bit signal:

wire [3:0]s1,in1,

Then you connected a 4-bit signal (in1) to a 1-bit port (S):

//     S
FA A1(in1,in2,s1,c1);

Since this is an unusual thing to do, your tool is doing the correct thing by issuing a warning message.

The width of the signal should match the width of the port. Based on your design requirements, you must decide which bit of in1 to connect to S. For example,

FA A1(in1[0],in2,s1,c1);

The same applies for the other warnings as well.

Upvotes: 1

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