CODEWITHSUNDEEP
verilog
josed2212
josed2212

Reputation: 31

Is there a way to create a verilog testbench for a module that instantiates other modules?

I am trying to create a test bench for the code shown below. In this testbench, I need to view the waveforms of the 4 bcd_counter modules, hundredths, tenths, ones, and tens. Is there a way to view the outputs for these in a single testbench even if they are being instantiated in the module "stopwatch"?

module stopwatch(CLOCK_50, BUTTON, HEX0, HEX1, HEX2, HEX2_DP, HEX3);

input CLOCK_50;

input [1:0] BUTTON;

output [0:6] HEX0, HEX1, HEX2, HEX3;

output reg HEX2_DP = 0;

wire ms_clk;

wire tenths_in, ones_in, tens_in;

wire [3:0] hundredths_bcd, tenths_bcd, ones_bcd, tens_bcd;

ms_clock ms_clock1(CLOCK_50, clk);

ms_clock_switched ms_clock_switched1(clk, BUTTON[0], ms_clk);

bcd_counter bcd_counter_hundredths(ms_clk, BUTTON[1], hundredths_bcd[3:0], tenths_in);

bcd_counter bcd_counter_tenths(tenths_in, BUTTON[1], tenths_bcd[3:0], ones_in);

bcd_counter bcd_counter_ones(ones_in, BUTTON[1], ones_bcd[3:0], tens_in);

bcd_counter bcd_counter_tens(tens_in, BUTTON[1], tens_bcd[3:0], );

seven_segment_decoder seven_segment_decoder_hundredths(hundredths_bcd[3:0], HEX0[0:6]);

seven_segment_decoder seven_segment_decoder_tenths(tenths_bcd[3:0], HEX1[0:6]);

seven_segment_decoder seven_segment_decoder_ones(ones_bcd[3:0], HEX2[0:6]);

seven_segment_decoder seven_segment_decoder_tens(tens_bcd[3:0], HEX3[0:6]);

endmodule



module seven_segment_decoder(bcd[3:0], HEX[0:6]);

input [3:0] bcd;

output [0:6] HEX;

reg [0:6] HEX;

always @ (bcd)

case(bcd)

4'b0000:HEX[0:6] = 7'b0000001;

4'b0001:HEX[0:6] = 7'b1001111;

4'b0010:HEX[0:6] = 7'b0010010;

4'b0011:HEX[0:6] = 7'b0000110;

4'b0100:HEX[0:6] = 7'b1001100;

4'b0101:HEX[0:6] = 7'b0100100;

4'b0110:HEX[0:6] = 7'b0100000;

4'b0111:HEX[0:6] = 7'b0001111;

4'b1000:HEX[0:6] = 7'b0000000;

4'b1001:HEX[0:6] = 7'b0001100;

default: HEX[0:6] = 7'b1111111; endcase

endmodule



module ms_clock_switched(ms_clock, control, ms_clock_switched);

input ms_clock, control;

output ms_clock_switched;

reg ms_clock_switched;

reg state; //0 paused, 1 active

//Basic state machine for toggleing the clock

always @ (negedge control)

state <= ~state;

always @ (ms_clock)

begin

if (state == 0)

ms_clock_switched <= 0;

else

ms_clock_switched <= ms_clock;

end

endmodule



module ms_clock(clock, ms_clock);

input clock;

output ms_clock;

reg ms_clock;

reg [0:17] count;

//Generate 100 Hz clock from a 50 mHz clock input

always @ (posedge clock)

begin

count <= count + 1;

if (count == 250000)

begin

ms_clock <= ~ms_clock;

count <= 0;

end

end

endmodule



module bcd_counter(clock, reset, bcd, next);

input clock, reset;

output bcd, next;

reg [3:0] bcd;

reg next;

wire not_reset;

not(not_reset, reset);

always @(posedge clock or posedge not_reset)

begin

if (not_reset == 1)

bcd <= 0;

else

begin

bcd <= bcd + 1;

next <= 0;

if (bcd > 8)

begin

bcd <= 0;

next <= 1;

end

end

end

endmodule

Here is what I have as a testbench so far, it does not work:

module stopwatch_tb();

    reg CLOCK, BUTTON[1:0];
    wire [15:0] count;
    
    stopwatch dut (CLOCK, BUTTON[1], BUTTON[0], HEX0, HEX1, HEX2, HEX2_DP, HEX3);
        
        initial begin
            CLOCK <= 1'b0;
            BUTTON[0] <= 1'b1;
        end
        
        always
        #1 CLOCK <= ~CLOCK;
        
        always begin
            #15 BUTTON[1] <= 1'b0;
            #3000 BUTTON[1] <= 1'b1;
        end
        
        always begin
            #25 BUTTON[0] <= 1'b1;
            #350 BUTTON[0] <= 1'b0;
        end
        
        initial 
            #3100 $stop;
            
        endmodule

Upvotes: 0

Views: 492

Answers (1)

Serge
Serge

Reputation: 12364

You have not provided a way which you use to generate waveforms. In general, a standard verilog vcd $dumpvars allows specifying which signals to dump as waveforms. It is all in documentation. So do other waveform dumpers.

As for just examining a value in a module hierarchy Verilog has cross-module references or XMRs. These are hierarchical references and allow accessing any signal across module hierarchy. For example, to examine the bcd signal within the bcd_counter in your test bench module you can do the following:

$display(
     dut.bcd_counter_ones.bcd, 
     dut.bcd_counter_tenths.bcd, 
     ...);

The hierarchy paths are expressed in terms of the instance names. I think that this is what you asked about.

Of course, the other way around is to place a part of your test bench as an initial block in the module which you are examining, i.e., bcd_counter.

Upvotes: 1

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