CODEWITHSUNDEEP
system-verilog-assertions
Umang Angrish
Umang Angrish

Reputation: 11

Trouble with assertion for check for a variable not to change between a handshake signal

I am trying to create an assertion property that checks if a 16-bit variable num should not change between a valid from the master until we receive a ready from a slave

what I have so far is

property check_num_change;
  logic [15:0] v;
  @(posedge clk) (($rose(valid) , v= num) |=> num == v until_with $rose(ready));
endproperty

currently, this is not working as intended. the assertion is not even passing or failing.

I need to know a better way to do this.

note: the working is that num should not change in between a valid and its corresponding ready.

If any of you have any idea about it or have faced a similar problem, and let me know, I would appreciate that much.

Thanks in advance for the help!

Upvotes: 0

Views: 671

Answers (1)

Arun D'souza
Arun D'souza

Reputation: 202

Here's my version:

  assert property(@(posedge clk) valid && !$past(ready) |-> $stable(num));

Look for valid, and if the previous value of ready is not high, then make sure num is stable between the previous and current clock cycle.

Example on EDA Playground: https://www.edaplayground.com/x/6jUt#

Upvotes: 0

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