CODEWITHSUNDEEP
verilogvivado
NotAProgrammer
NotAProgrammer

Reputation: 67

Verilog - Assign an output that lasts more than 1 clock cycle

I have designed a simple sequence detector that works, but I am wondering how I can edit it so that the valid_password outputs as high for 3 clock cycles regardless of input changes. Here is what I've set my valid_password as:

assign valid_password = (present_state==s8)&(pass_in==3);

I know I've set it so that it only outputs high for this one specific state and input value but I am very new to this so any advice for recommended syntax's I should look for is very appreciated.

Upvotes: 0

Views: 917

Answers (1)

Pradyuman Bissa
Pradyuman Bissa

Reputation: 191

Try a delay register. Here trigger register will assert high when valid_password condition hits. This is then passed on for two cycles.

reg [2:0] trigger;

always@(posedge clk or negedge rstn)
begin
 if(!rstn)
  trigger <= 'd0;
 else
 begin
  trigger[0] <= (present_state==s8) & (pass_in==3);
  trigger[1] <= trigger[0];
  trigger[2] <= trigger[1];
 end
end

 assign valid_password = ( (present_state==s8)&(pass_in==3) ) | trigger[0] | trigger[1] | trigger[2];

Upvotes: 1

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