CODEWITHSUNDEEP
verilogsystem-verilog
dror
dror

Reputation: 3

System verolog interface with parameters

I'm trying to build an interface to connect two modules. the interface is in the next format:

interface my_if #( 
    parameter H_WIDTH = 64,
    parameter L_WIDTH = 8
);
logic [H_WIDTH -1:0]  a;
logic [L_WIDTH -1:0]  b;
logic                 ready;
modport in ( input a, input b, output valid);
modport out( output a, output b, input ready);
endinterface;

I need to connect two modules using this interface, while I have different parameters of address and index for every connection (for example, 3 my_if interfaces are connecting my two modules, but every one of them has a different address and index params). how I can make this work?

Upvotes: 0

Views: 1137

Answers (1)

Serge
Serge

Reputation: 12354

Your question sounds like you have two modules which connected by 3 interfaces with different params. If I am correct in this guess, the answer is simple.

  1. To use any interface for connecting modules, it has to be instantiated with different correct params:
my_if #(64, 8) if64_8;
my_if #(32,4) if32_4;
my_if #(16,2) if16_2;

now the moduel must be used to handle an interface

module m1(my_if in1, my_if in2, my_if in3);
 // ...
endmodule
module m2(my_if out1, my_if out2, my_if out3);
  // ...
endmodule

and you can connect them:

  m1 m1 (if64_8.in, if32_4.in, if16_2.in);
  m2 m2 (if64_8.out, if32_4.out, if16_2.out);

Here is a compilable example

interface my_if #( 
    parameter H_WIDTH = 64,
    parameter L_WIDTH = 8
);
logic [H_WIDTH -1:0]  a;
logic [L_WIDTH -1:0]  b;
logic valid;
logic ready;
modport in ( input a, input b, output valid);
modport out( output a, output b, input ready);
endinterface

module top;
  my_if #(64, 8) if64_8();
  my_if #(32,4) if32_4();
  my_if #(16,2) if16_2();

  m1 m1 (if64_8.in, if32_4.in, if16_2.in);
  m2 m2 (if64_8.out, if32_4.out, if16_2.out);
endmodule

module m1(my_if in1, my_if in2, my_if in3);
  // ...
  initial begin
    $display("%0d, %0d, %0d", $bits(in1.a), $bits(in2.a), $bits(in3.a));
  end
endmodule
module m2(my_if out1, my_if out2, my_if out3);
  // ...
endmodule

The $display statement shows that the widths of the signals is different for every different 'in'.

Upvotes: 0

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