CODEWITHSUNDEEP
verilogsystem-verilog
None
None

Reputation: 2433

Different struct elements "written by continuous and procedural assignments"

Why do I get :

# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[0].subar[0]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[0].subar[1]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[0].subar[2]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[0].subar[3]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[1].subar[0]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[1].subar[1]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[1].subar[2]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[1].subar[3]' written by continuous and procedural assignments. See testbench.sv(19).

for this code:

module tb;

logic clk;

struct {
  struct {
    logic seq;
    logic assig;
    logic seq2;
  } subar [4];
} ar [2];


always_ff @(posedge clk) begin
  for (int i=0; i<2; i++) begin
    for (int j=0; j<4; j++) begin
      ar[i].subar[j].seq <= '1;
    end
  end
end

generate
  for (genvar i=0; i<2; i++) begin
    for (genvar j=0; j<4; j++) begin
      assign ar[i].subar[j].assig = '1;
    end
  end
endgenerate

always_ff @(posedge clk) begin
  for (int i=0; i<2; i++) begin
    for (int j=0; j<4; j++) begin
      ar[i].subar[j].seq2 <= '1;
    end
  end
end

endmodule

All the three logics are independent inside the structure and they aren't assigned in two different blocs.

EDA Playground: https://www.edaplayground.com/x/qYZ9

Replacing the generate/assign with always_comb

always_comb begin
  for (int i=0; i<2; i++) begin
    for (int j=0; j<4; j++) begin
      ar[i].subar[j].assig = ar[i].subar[j].seq;
    end
  end
end

Replacing the generate with assign with an always_comb bloc gives a different result because all the *.seq signals are X.

Each assig = seq are all independent between each i and j iteration.

Why is this invalid?

Not being able to use a structure to group signals is excessively annoying...

Upvotes: 0

Views: 377

Answers (1)

dave_59
dave_59

Reputation: 42698

The error message is because of the rather pessimistic definition of Longest static prefix in section 11.5.3 of the IEEE 1800-2017 SystemVerilog LRM. Basically, since i is a variable index, the long static prefix of ar[i] is ar and any array or struct selects succeeding that are irrelevant. Tools have been treating this more optimistically, but that has been a gradual process.

You can either suppress the error globally, or rewrite the code moving the for loop out of the block into a generate-for loop.

module tb;

logic clk;

struct {
  struct {
    logic seq;
    logic assig;
    logic seq2;
  } subar [4];
} ar [2];

for (genvar  i=0; i<2; i++) begin
  for (genvar  j=0; j<4; j++) begin
always_ff @(posedge clk) begin
      ar[i].subar[j].seq <= '1;
    end
  end
end

  for (genvar i=0; i<2; i++) begin
    for (genvar j=0; j<4; j++) begin
      assign ar[i].subar[j].assig = '1;
    end
  end

for (genvar  i=0; i<2; i++) begin
  for (genvar  j=0; j<4; j++) begin
    always_ff @(posedge clk) begin
      ar[i].subar[j].seq2 <= '1;
    end
  end
end

endmodule

Upvotes: 2

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