CODEWITHSUNDEEP
verilogxilinxxilinx-ise
testtest123321
testtest123321

Reputation: 35

How to change a register value without adding it to the sensitivity list?

module main(input A, B, C,button,clk100mhz,output [7:0]seg,[7:0]an);
    reg [3:0] D0;
    reg [3:0] D1;
    reg [3:0] D2;
    reg [7:0] Y;
    DISP7SEG m1 (clk100mhz, D0, D1, D2, 4'b0000,4'b0000,4'b0000,4'b0000,4'b0000, 1'b0, 1'b0, 1'b0,1'b0,1'b0, 1'b0, seg, an);
    always@(button)
    begin
        if (button)
        if (A+B+C == 1'b1)//only one switch 
        if (Y < 7'd75)
        begin
            Y = Y + {A,B,C} * 5'd25;
            D0 = Y      % 10;
            D1 = (Y/10)  %10;
            D2 = (Y/100) %10;
        end
    end
endmodule

this is supposed be a basic adder up to 75 with a multiplication by 25 at every step

for example if ABC is 001 I should get 25 -> 50 -> 75 in reg Y after every button press, the problem is that xilinx ISE gives this error

WARNING:HDLCompiler:91 - "main.v" Line 33: Signal Y missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result.

so it becomes an infinite loop every time Y is changed it triggers the always block and changes it again and so on How am I supposed to do this without triggering this error or to somehow stop the tool from adding it to the sensitivity list

Upvotes: -1

Views: 270

Answers (1)

Eric W
Eric W

Reputation: 1

As @toolic and @Serge said, you need to use a clocked always block. Take a look at this article: https://www.chipverify.com/verilog/verilog-always-sequential-logic

The always block should be sensitive to (posedge clk100mhz). Every rising edge of the clock, it will run and increment Y if all your "if" conditions are met.

Then Y will increment for every clock that button is held down. This probably isn't the desired behavior so consider adding some logic that only triggers once for each button press.

Upvotes: -1

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