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adabella asi
adabella asi

Reputation: 99

How to add integer based vhdl inout signal to ucf file

I'm completely new to VHDL and I wrote a code that's supposed to be a 16*4 RAM memory.I wrote a VHDL and VHDL testbench for it and I tried to add a user constraints file(ucf) to it and everything seems fine,except that It gives error on four of my pins.Here is my code:

NET "a<0>" LOC = "p51";
NET "a<1>" LOC = "p59";
NET "a<2>" LOC = "p48";
NET "a<3>" LOC = "p55";

NET "a<0>" LOC = "p51";
NET "a<1>" LOC = "p59";
NET "a<2>" LOC = "p48";
NET "a<3>" LOC = "p55";

NET "di<0>" LOC = "p66";
NET "di<1>" LOC = "p56";
NET "di<2>" LOC = "p57";
NET "di<3>" LOC = "p58";

NET "do<0>" LOC = "p78";
NET "do<1>" LOC = "p75";
NET "do<2>" LOC = "p64";
NET "do<3>" LOC = "p74";

The VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity memory is
    Port(
        clk: in STD_LOGIC;
        we: in STD_LOGIC;
        a:inout integer RANGE 0 to 3; --read and write address-
        di: in STD_LOGIC_VECTOR(3 downto 0);
        do: out STD_LOGIC_VECTOR(3 downto 0)
    );
end memory;

architecture Behavioral of memory is
    TYPE mem IS ARRAY(0 TO 7) OF std_logic_vector(3 DOWNTO 0);
   SIGNAL ram_block : mem ;
begin
    process(clk)
        begin
            if(clk'event and clk='1') then
                if(we='1') then
                    ram_block(a) <= di;
            
                else
                     do <= ram_block(a);
                 end if;
            end if;
        end process;


end Behavioral;

And these are my errors:

ERROR:ConstraintSystem:59 - Constraint <NET "a<2>" LOC = "p48";>
[memoryPin.ucf(3)]: NET "a<2>" not found. Please verify that:

  1. The specified design element actually exists in the original design.
  2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <NET "a<3>" LOC = "p55";> [memoryPin.ucf(4)]: NET "a<3>" not found. Please verify that:
  3. The specified design element actually exists in the original design.
  4. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <NET "a<2>" LOC = "p48";> [memoryPin.ucf(8)]: NET "a<2>" not found. Please verify that:
  5. The specified design element actually exists in the original design.
  6. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <NET "a<3>" LOC = "p55";> [memoryPin.ucf(9)]: NET "a<3>" not found. Please verify that:
  7. The specified design element actually exists in the original design.
  8. The specified object is spelled correctly in the constraint source file.

I tried removing the entire 'a' pins from the ucf file,and the implement design seemed to work,however,as I said,I'm new to VHDL,and I don't quite understand the concept of the ucf file.I don't know if it is supposed to work correctly or not.I'd be glad if you helped.

Upvotes: 1

Views: 162

Answers (1)

Tony Liechty
Tony Liechty

Reputation: 19

My best recommendation would be to keep top level signals in your vhdl to be of type std_logic and std_logic_vector. Integers in theory could be encoded in a number of ways, and thus the mapping to physical pins could be different. For example, integers could be binary encoded, grey encoded, signed or unsigned, and the physical pins would have different values for each encoding.

A std_logic_vector however is just an array of wires, and has just one meaning, on or off for each index. Though the original question is how to add an integer to the ucf, I'd instead recommend converting it to a std_logic_vector at the top level vhdl file with something as follows:

For outputs, you could do:

out <= std_logic_vector(to_unsigned(my_int,my_slv'length))

For inputs you could do:

my_int <= to_integer(unsigned(a))

Notice also how this forces stating if signal is unsigned or signed.

Upvotes: 0

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